Re: [PATCH v5 2/4] target/riscv: implement Zicboz extension

[Richard Henderson]

On 2/15/23 10:59, Daniel Henrique Barboza wrote:
> +    mem = probe_access(env, address, cbozlen, MMU_DATA_STORE,
> +                       cpu_mmu_index(env, false), ra);
> +
> +    /* Zero the block */
> +    memset(mem, 0, cbozlen);

Will crash if address does not resolve to ram.

According to page 16, you need to store zeros even if the memory is not cacheable.  C.f. 
target/arm/helper-a64.c HELPER(dc_zva) or target/s390x/tcg/mem_helper.c do_access_memset.

While re-reading the ARM code, I remembered that the ARM dc.zva instruction is required to 
produce original unmasked address on a page fault, thus the little dance with two calls to 
probe_write.

I don't immediately see language in the risc-v spec beyond "CMO instructions do not 
generate address misaligned exceptions."


r~