Re: [PATCH 11/11] target/riscv/cpu: remove CPUArchState^features and friends

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> The attribute is no longer used since we can retrieve all the enabled
> features in the hart by using cpu->cfg instead.
>
> Remove env->feature, riscv_feature() and riscv_set_feature(). We also
> need to bump vmstate_riscv_cpu version_id and minimal_version_id since
> 'features' is no longer being migrated.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li
> ---
>   target/riscv/cpu.h     | 12 ------------
>   target/riscv/machine.c |  5 ++---
>   2 files changed, 2 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 83a9fa38d9..6290c6d357 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -173,8 +173,6 @@ struct CPUArchState {
>       /* 128-bit helpers upper part return value */
>       target_ulong retxh;
>   
> -    uint32_t features;
> -
>   #ifdef CONFIG_USER_ONLY
>       uint32_t elf_flags;
>   #endif
> @@ -525,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env, 
> target_ulong ext)
>       return (env->misa_ext & ext) != 0;
>   }
>   
> -static inline bool riscv_feature(CPURISCVState *env, int feature)
> -{
> -    return env->features & (1ULL << feature);
> -}
> -
> -static inline void riscv_set_feature(CPURISCVState *env, int feature)
> -{
> -    env->features |= (1ULL << feature);
> -}
> -
>   #include "cpu_user.h"
>   
>   extern const char * const riscv_int_regnames[];
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 67e9e56853..9c455931d8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
>   
>   const VMStateDescription vmstate_riscv_cpu = {
>       .name = "cpu",
> -    .version_id = 6,
> -    .minimum_version_id = 6,
> +    .version_id = 7,
> +    .minimum_version_id = 7,
>       .post_load = riscv_cpu_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = {
>           VMSTATE_UINT32(env.misa_ext, RISCVCPU),
>           VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
>           VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
> -        VMSTATE_UINT32(env.features, RISCVCPU),
>           VMSTATE_UINTTL(env.priv, RISCVCPU),
>           VMSTATE_UINTTL(env.virt, RISCVCPU),
>           VMSTATE_UINT64(env.resetvec, RISCVCPU),