[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC 24/52] loongarch: Replace MachineState.smp access with topology hel
From: |
Zhao Liu |
Subject: |
[RFC 24/52] loongarch: Replace MachineState.smp access with topology helpers |
Date: |
Mon, 13 Feb 2023 17:50:07 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
When MachineState.topo is introduced, the topology related structures
become complicated. So we wrapped the access to topology fields of
MachineState.topo into some helpers, and we are using these helpers
to replace the use of MachineState.smp.
Before loongarch supports hybrid, here we use smp-specific interface to
get "threads per core" and "cores per cluster".
For other cases, it's straightforward to replace topology access with
wrapped generic interfaces.
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
hw/loongarch/acpi-build.c | 4 ++--
hw/loongarch/fw_cfg.c | 4 ++--
hw/loongarch/virt.c | 30 ++++++++++++++++--------------
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index f551296a0e07..87fa5f0836f8 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -116,7 +116,7 @@ build_madt(GArray *table_data, BIOSLinker *linker,
LoongArchMachineState *lams)
build_append_int_noprefix(table_data, 0, 4);
build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
- for (i = 0; i < ms->smp.cpus; i++) {
+ for (i = 0; i < machine_topo_get_cpus(ms); i++) {
/* Processor Core Interrupt Controller Structure */
build_append_int_noprefix(table_data, 17, 1); /* Type */
build_append_int_noprefix(table_data, 15, 1); /* Length */
@@ -168,7 +168,7 @@ build_srat(GArray *table_data, BIOSLinker *linker,
MachineState *machine)
build_append_int_noprefix(table_data, 1, 4); /* Reserved */
build_append_int_noprefix(table_data, 0, 8); /* Reserved */
- for (i = 0; i < ms->smp.cpus; ++i) {
+ for (i = 0; i < machine_topo_get_cpus(ms); ++i) {
/* Processor Local APIC/SAPIC Affinity Structure */
build_append_int_noprefix(table_data, 0, 1); /* Type */
build_append_int_noprefix(table_data, 16, 1); /* Length */
diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c
index f15a17416c48..a9c1762a1681 100644
--- a/hw/loongarch/fw_cfg.c
+++ b/hw/loongarch/fw_cfg.c
@@ -20,8 +20,8 @@ static void fw_cfg_boot_set(void *opaque, const char
*boot_device,
FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms)
{
FWCfgState *fw_cfg;
- int max_cpus = ms->smp.max_cpus;
- int smp_cpus = ms->smp.cpus;
+ int max_cpus = machine_topo_get_max_cpus(ms);
+ int smp_cpus = machine_topo_get_cpus(ms);
fw_cfg = fw_cfg_init_mem_wide(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8,
VIRT_FWCFG_BASE + 16, &address_space_memory);
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 66be9250684e..475b82d283bf 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -152,7 +152,9 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState
*lams)
{
int num;
const MachineState *ms = MACHINE(lams);
- int smp_cpus = ms->smp.cpus;
+ int smp_cpus = machine_topo_get_cpus(ms);
+ int smp_cores = machine_topo_get_smp_cores(ms);
+ int smp_threads = machine_topo_get_smp_threads(ms);
qemu_fdt_add_subnode(ms->fdt, "/cpus");
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
@@ -180,17 +182,17 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState
*lams)
char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
char *map_path;
- if (ms->smp.threads > 1) {
+ if (smp_threads > 1) {
map_path = g_strdup_printf(
"/cpus/cpu-map/socket%d/core%d/thread%d",
- num / (ms->smp.cores * ms->smp.threads),
- (num / ms->smp.threads) % ms->smp.cores,
- num % ms->smp.threads);
+ num / (smp_cores * smp_threads),
+ (num / smp_threads) % smp_cores,
+ num % smp_threads);
} else {
map_path = g_strdup_printf(
"/cpus/cpu-map/socket%d/core%d",
- num / ms->smp.cores,
- num % ms->smp.cores);
+ num / smp_cores,
+ num % smp_cores);
}
qemu_fdt_add_path(ms->fdt, map_path);
qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
@@ -553,7 +555,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
LoongArchCPU *lacpu;
CPULoongArchState *env;
CPUState *cpu_state;
- int cpu, pin, i, start, num;
+ int cpu, pin, i, start, num, smp_cpus = machine_topo_get_cpus(ms);
ipi = qdev_new(TYPE_LOONGARCH_IPI);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
@@ -582,7 +584,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
* | UARTs | | Devices | | Devices |
* +--------+ +---------+ +---------+
*/
- for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ for (cpu = 0; cpu < smp_cpus; cpu++) {
cpu_state = qemu_get_cpu(cpu);
cpudev = DEVICE(cpu_state);
lacpu = LOONGARCH_CPU(cpu_state);
@@ -607,7 +609,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
* connect ext irq to the cpu irq
* cpu_pin[9:2] <= intc_pin[7:0]
*/
- for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
+ for (cpu = 0; cpu < smp_cpus; cpu++) {
cpudev = DEVICE(qemu_get_cpu(cpu));
for (pin = 0; pin < LS3A_INTC_IP; pin++) {
qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
@@ -736,7 +738,7 @@ static void
loongarch_direct_kernel_boot(LoongArchMachineState *lams)
kernel_addr = load_kernel_info();
if (!machine->firmware) {
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < machine_topo_get_cpus(machine); i++) {
lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
lacpu->env.load_elf = true;
lacpu->env.elf_address = kernel_addr;
@@ -753,7 +755,7 @@ static void loongarch_init(MachineState *machine)
uint64_t highram_size = 0;
MemoryRegion *address_space_mem = get_system_memory();
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
- int i;
+ int i, smp_cpus = machine_topo_get_cpus(machine);
hwaddr fdt_base;
if (!cpu_model) {
@@ -771,7 +773,7 @@ static void loongarch_init(MachineState *machine)
}
create_fdt(lams);
/* Init CPUs */
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < smp_cpus; i++) {
cpu_create(machine->cpu_type);
}
fdt_add_cpu_nodes(lams);
@@ -846,7 +848,7 @@ static void loongarch_init(MachineState *machine)
}
fdt_add_flash_node(lams);
/* register reset function */
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < smp_cpus; i++) {
lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
qemu_register_reset(reset_load_elf, lacpu);
}
--
2.34.1
- [RFC 20/52] s390x: Replace MachineState.smp access with topology helpers, (continued)
- [RFC 20/52] s390x: Replace MachineState.smp access with topology helpers, Zhao Liu, 2023/02/13
- [RFC 21/52] ppc: Replace MachineState.smp access with topology helpers, Zhao Liu, 2023/02/13
- [RFC 22/52] riscv: Replace MachineState.smp access with topology helpers, Zhao Liu, 2023/02/13
- [RFC 23/52] arm: Replace MachineState.smp access with topology helpers, Zhao Liu, 2023/02/13
- [RFC 25/52] mips: Replace MachineState.smp access with topology helpers, Zhao Liu, 2023/02/13
- [RFC 26/52] hw: Replace MachineState.smp access with topology helpers for all remaining archs, Zhao Liu, 2023/02/13
- [RFC 27/52] test/test-smp-parse: Check fields of MachineState.topo.smp, Zhao Liu, 2023/02/13
- [RFC 28/52] hw/core/machine: Remove support of MachineState.smp, Zhao Liu, 2023/02/13
- [RFC 24/52] loongarch: Replace MachineState.smp access with topology helpers,
Zhao Liu <=
- [RFC 30/52] i386: Drop nr_dies and nr_modules CPUX86State, Zhao Liu, 2023/02/13
- [RFC 29/52] hw/core/cpu: Introduce TopologyState in CPUState, Zhao Liu, 2023/02/13
- [RFC 31/52] i386/cpu: Use CPUState.topo to replace X86CPUTopoInfo to get topology info, Zhao Liu, 2023/02/13
- [RFC 32/52] i386: Rename X86CPUTopoInfo and its members to reflect relationship with APIC ID, Zhao Liu, 2023/02/13
- [RFC 35/52] i386: Support APIC ID topology for hybrid CPU topology, Zhao Liu, 2023/02/13
- [RFC 33/52] i386: Rename init_topo_info() to init_apic_topo_info(), Zhao Liu, 2023/02/13