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[PATCH RESEND 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[
From: |
Zhao Liu |
Subject: |
[PATCH RESEND 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] |
Date: |
Mon, 13 Feb 2023 17:36:24 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache
topology for amd CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x8000001D].EAX[bits 25:14].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d691c02e3c06..5816dc99b1d4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -355,20 +355,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- uint32_t sharing_apic_ids;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
-
- /* L3 is shared among multiple cores */
- if (cache->level == 3) {
- sharing_apic_ids = 1 << apicid_die_offset(topo_info);
- } else {
- sharing_apic_ids = 1 << apicid_core_offset(topo_info);
- }
- *eax |= (sharing_apic_ids - 1) << 14;
+ *eax |= max_processor_ids_for_cache(cache, topo_info) << 14;
assert(cache->line_size > 0);
assert(cache->partitions > 0);
--
2.34.1
- Re: [PATCH RESEND 10/18] i386: Update APIC ID parsing rule to support module level, (continued)
- [PATCH RESEND 11/18] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/02/13
- [PATCH RESEND 12/18] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2023/02/13
- [PATCH RESEND 13/18] hw/i386/pc: Support smp.clusters for x86 PC machine, Zhao Liu, 2023/02/13
- [PATCH RESEND 14/18] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/02/13
- [PATCH RESEND 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14], Zhao Liu, 2023/02/13
- [PATCH RESEND 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14],
Zhao Liu <=
- [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/02/13
- Re: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, wangyanan (Y), 2023/02/16
- Re: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, wangyanan (Y), 2023/02/16
- Re: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/02/17
- Re: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, wangyanan (Y), 2023/02/17
- Re: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/02/19
- Re: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, wangyanan (Y), 2023/02/19