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[PATCH] target/i386: Fix exception classes for SSE/AVX instructions.
From: |
Ricky Zhou |
Subject: |
[PATCH] target/i386: Fix exception classes for SSE/AVX instructions. |
Date: |
Sun, 12 Feb 2023 00:28:12 -0800 |
Fix the exception classes for some SSE/AVX instructions to match what is
documented in the Intel manual.
Most of these changes have no functional effect on the behavior that
qemu implements (primarily >= 16-byte memory alignment checks). For
example, since qemu does not implement the AC flag, there is no
difference in behavior between Exception Classes 4 and 5 for
instructions where the SSE version only takes <16 byte memory operands.
There is one functional change:
Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class
4 (only requiring alignment for legacy SSE instructions). This changes
them to Exception Class 1 (always requiring memory alignment), as
documented in the Intel manual.
Signed-off-by: Ricky Zhou <ricky@rzhou.org>
---
target/i386/tcg/decode-new.c.inc | 79 ++++++++++++++++----------------
1 file changed, 40 insertions(+), 39 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index d5fd8d965c..a9060c3268 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -237,7 +237,7 @@ static void decode_group14(DisasContext *s, CPUX86State
*env, X86OpEntry *entry,
static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F6F[4] = {
- X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* movq */
+ X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa
*/
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu
*/
{},
@@ -274,9 +274,9 @@ static void decode_0F78(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
{
static const X86OpEntry opcodes_0F78[4] = {
{},
- X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)),
+ X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /*
AMD extension */
{},
- X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)),
+ X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), /*
AMD extension */
};
*entry = *decode_by_prefix(s, opcodes_0F78);
}
@@ -284,9 +284,9 @@ static void decode_0F78(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
if (s->prefix & PREFIX_REPNZ) {
- entry->gen = gen_INSERTQ_r;
+ entry->gen = gen_INSERTQ_r; /* AMD extension */
} else if (s->prefix & PREFIX_DATA) {
- entry->gen = gen_EXTRQ_r;
+ entry->gen = gen_EXTRQ_r; /* AMD extension */
} else {
entry->gen = NULL;
};
@@ -306,7 +306,7 @@ static void decode_0F7E(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F7F[4] = {
- X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx), /* movq */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu
*/
{},
@@ -639,15 +639,15 @@ static void decode_0F10(DisasContext *s, CPUX86State
*env, X86OpEntry *entry, ui
static const X86OpEntry opcodes_0F10_reg[4] = {
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
- X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex4),
- X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex4), /* MOVSD */
+ X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5),
+ X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */
};
static const X86OpEntry opcodes_0F10_mem[4] = {
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS
*/
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD
*/
- X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex4),
- X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex4),
+ X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5),
+ X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5),
};
if ((get_modrm(s, env) >> 6) == 3) {
@@ -660,17 +660,17 @@ static void decode_0F10(DisasContext *s, CPUX86State
*env, X86OpEntry *entry, ui
static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F11_reg[4] = {
- X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
- X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
- X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex4),
- X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex4), /* MOVSD */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
+ X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5),
+ X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */
};
static const X86OpEntry opcodes_0F11_mem[4] = {
- X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
- X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
- X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4),
- X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
+ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
+ X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5),
+ X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */
};
if ((get_modrm(s, env) >> 6) == 3) {
@@ -687,16 +687,16 @@ static void decode_0F12(DisasContext *s, CPUX86State
*env, X86OpEntry *entry, ui
* Use dq for operand for compatibility with gen_MOVSD and
* to allow VEX128 only.
*/
- X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPS */
- X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPD */
+ X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */
+ X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */
X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
- X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex4 cpuid(SSE3)), /*
qq if VEX.256 */
+ X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3)), /*
qq if VEX.256 */
};
static const X86OpEntry opcodes_0F12_reg[4] = {
- X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex4),
- X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex4), /* MOVLPD */
+ X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7),
+ X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD */
X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
- X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
+ X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)),
};
if ((get_modrm(s, env) >> 6) == 3) {
@@ -716,15 +716,15 @@ static void decode_0F16(DisasContext *s, CPUX86State
*env, X86OpEntry *entry, ui
* Operand 1 technically only reads the low 64 bits, but uses dq so
that
* it is easier to check for op0 == op1 in an endianness-neutral
manner.
*/
- X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPS */
- X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPD */
+ X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */
+ X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */
X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
{},
};
static const X86OpEntry opcodes_0F16_reg[4] = {
/* Same as above, operand 1 could be Hq if it wasn't for big-endian.
*/
- X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex4),
- X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex4), /* MOVHPD */
+ X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7),
+ X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */
X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
{},
};
@@ -750,8 +750,9 @@ static void decode_0F2A(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F2B[4] = {
- X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */
- X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */
+ X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPS */
+ X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPD */
+ /* AMD extensions */
X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /*
MOVNTSS */
X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /*
MOVNTSD */
};
@@ -813,7 +814,7 @@ static void decode_0FE6(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
static const X86OpEntry opcodes_0FE6[4] = {
{},
X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2),
- X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex2),
+ X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5),
X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2),
};
*entry = *decode_by_prefix(s, opcodes_0FE6);
@@ -831,17 +832,17 @@ static const X86OpEntry opcodes_0F[256] = {
[0x10] = X86_OP_GROUP0(0F10),
[0x11] = X86_OP_GROUP0(0F11),
[0x12] = X86_OP_GROUP0(0F12),
- [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex4 p_00_66),
+ [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_66),
[0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66),
[0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66),
[0x16] = X86_OP_GROUP0(0F16),
/* Incorrectly listed as Mq,Vq in the manual */
- [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex4 p_00_66),
+ [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66),
[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
- [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
- [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3),
- [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3),
+ [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2), /* sqrtps */
+ [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /*
rsqrtps */
+ [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /*
rcpps */
[0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand
*/
[0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn
*/
[0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
@@ -871,15 +872,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x2B] = X86_OP_GROUP0(0F2B),
[0x2C] = X86_OP_GROUP0(0F2C),
[0x2D] = X86_OP_GROUP0(0F2D),
- [0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_66),
- [0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_66),
+ [0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex3 p_00_66),
+ [0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex3 p_00_66),
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
[0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
- [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2), /* CVTPS2PD */
[0x5b] = X86_OP_GROUP0(0F5B),
[0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
--
2.39.1
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Ricky Zhou <=