Re: [PATCH 18/22] target/arm: Add GPC syndrome

[Peter Maydell]

On Tue, 24 Jan 2023 at 00:02, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The function takes the fields as filled in by
> the Arm ARM pseudocode for TakeGPCException.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/syndrome.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
> index 73df5e3793..3fa926d115 100644
> --- a/target/arm/syndrome.h
> +++ b/target/arm/syndrome.h
> @@ -49,6 +49,7 @@ enum arm_exception_class {
>      EC_SYSTEMREGISTERTRAP     = 0x18,
>      EC_SVEACCESSTRAP          = 0x19,
>      EC_SMETRAP                = 0x1d,
> +    EC_GPC                    = 0x1e,
>      EC_INSNABORT              = 0x20,
>      EC_INSNABORT_SAME_EL      = 0x21,
>      EC_PCALIGNMENT            = 0x22,
> @@ -237,6 +238,14 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int 
> rm)
>          (cv << 24) | (cond << 20) | rm;
>  }
>
> +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc,
> +                               int cm, int s1ptw, int wnr, int fsc)
> +{
> +    return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21)
> +            | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7)
> +            | (wnr << 6) | fsc;
> +}

I guess we can add VNCR (bit 13) when we implement FEAT_NV2...

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM