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Re: [PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation
From: |
Bastian Koppelmann |
Subject: |
Re: [PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation |
Date: |
Wed, 8 Feb 2023 10:16:55 +0100 |
On Thu, Feb 02, 2023 at 03:55:53PM +0000, Anton Kochkov wrote:
> ------- Original Message -------
> On Friday, January 13th, 2023 at 5:03 AM, Bastian Koppelmann
> <kbastian@mail.uni-paderborn.de> wrote:
>
>
> >
> >
> > On Thu, Jan 12, 2023 at 02:24:02PM +0000, Anton Kochkov wrote:
> >
> > > Signed-off-by: Eitan Eliahu eitan_eliahu@hotmail.com
> > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652
> > > ---
> > > target/tricore/translate.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> > > index df9e46c649..b2a5e11778 100644
> > > --- a/target/tricore/translate.c
> > > +++ b/target/tricore/translate.c
> > > @@ -3878,7 +3878,7 @@ static void decode_sro_opc(DisasContext *ctx, int
> > > op1)
> > > gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
> > > break;
> > > case OPC1_16_SRO_LD_H:
> > > - gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
> > > + gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
> > > break;
> > > case OPC1_16_SRO_LD_W:
> > > gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
> > > --
> > > 2.39.0
> >
> >
> > Reviewed-by: Bastian Koppelmann kbastian@mail.uni-paderborn.de
> >
> >
> > As Phil said, good catch. I added it to my TriCore queue.
> >
> > I saw on the bugtracker that you have testcase. Are you interested in
> > adding it to
> > tests/tcg/tricore?
>
> Sorry for the late answer - it's not me who initially opened the original
> issue thus I don't have a test case.
No worries. I created a test myself (see
20230203132132.511254-1-kbastian@mail.uni-paderborn.de/">https://lore.kernel.org/qemu-devel/20230203132132.511254-1-kbastian@mail.uni-paderborn.de/)
Cheers,
Bastian
>