Re: [PATCH v2] target/riscv: fix ctzw behavior

[Alistair Francis]

On Sat, Feb 4, 2023 at 6:25 PM Vladimir Isaev
<vladimir.isaev@syntacore.com> wrote:
>
> According to spec, ctzw should work with 32-bit register, not 64.
>
> For example, previous implementation returns 33 for (1<<33) input
> when the new one returns 32.
>
> Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> v2:
>    - Use simpler solution suggested by Richard Henderson
> ---
>  target/riscv/insn_trans/trans_rvb.c.inc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index e2b8329f1e5b..990bc94b9840 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -401,6 +401,7 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
>  {
>      REQUIRE_64BIT(ctx);
>      REQUIRE_ZBB(ctx);
> +    ctx->ol = MXL_RV32;
>      return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
>  }
>
> --
> 2.39.1
>
>