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[PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max'
From: |
Peter Maydell |
Subject: |
[PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max' |
Date: |
Fri, 3 Feb 2023 14:29:27 +0000 |
Update the ID registers for TCG's '-cpu max' to report the
presence of FEAT_FGT Fine-Grained Traps support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index b87e064d9dc..2062d712610 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -30,6 +30,7 @@ the following architecture extensions:
- FEAT_ETS (Enhanced Translation Synchronization)
- FEAT_EVT (Enhanced Virtualization Traps)
- FEAT_FCMA (Floating-point complex number instructions)
+- FEAT_FGT (Fine-Grained Traps)
- FEAT_FHM (Floating-point half-precision multiplication instructions)
- FEAT_FP16 (Half-precision floating-point data processing)
- FEAT_FRINTTS (Floating-point to integer instructions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0e021960fb5..4066950da15 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1224,6 +1224,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
--
2.34.1
- [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11, (continued)
- [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 18/33] target/arm: Define the FEAT_FGT registers, Peter Maydell, 2023/02/03
- [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17, Peter Maydell, 2023/02/03
- [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps, Peter Maydell, 2023/02/03
- [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps, Peter Maydell, 2023/02/03
- [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus, Peter Maydell, 2023/02/03
- [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic, Peter Maydell, 2023/02/03
- [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier, Peter Maydell, 2023/02/03
- [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47, Peter Maydell, 2023/02/03
- [PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max',
Peter Maydell <=
- Re: [PULL 00/33] target-arm queue, Peter Maydell, 2023/02/03