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[PATCH 32/39] target/riscv: add zvkg cpu property
From: |
Lawrence Hunter |
Subject: |
[PATCH 32/39] target/riscv: add zvkg cpu property |
Date: |
Thu, 2 Feb 2023 12:42:23 +0000 |
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a3b08e9d27..6fded328f8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -101,6 +101,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
+ ISA_EXT_DATA_ENTRY(zvkg, true, PRIV_VERSION_1_12_0, ext_zvkg),
ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns),
@@ -802,7 +803,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
* in qemu
*/
if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknha ||
- cpu->cfg.ext_zvksh) &&
+ cpu->cfg.ext_zvksh || cpu->cfg.ext_zvkg) &&
!(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v)) {
error_setg(
errp, "Vector crypto extensions require V or Zve* extensions");
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 92624bfc57..b3b1174d74 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,6 +462,7 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
bool ext_zvkb;
+ bool ext_zvkg;
bool ext_zvknha;
bool ext_zvknhb;
bool ext_zvkns;
--
2.39.1
- [PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support, (continued)
- [PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 13/39] target/riscv: Add vaesef.vs decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 14/39] target/riscv: Add vaesdf.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 18/39] target/riscv: Add vaesz.vs decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 19/39] target/riscv: Add vaesem.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 24/39] target/riscv: add zvknh cpu properties, Lawrence Hunter, 2023/02/02
- [PATCH 39/39] target/riscv: Expose Zvksed property, Lawrence Hunter, 2023/02/02
- [PATCH 34/39] target/riscv: expose zvkg cpu property, Lawrence Hunter, 2023/02/02
- [PATCH 31/39] target/riscv: expose zvksh cpu property, Lawrence Hunter, 2023/02/02
- [PATCH 32/39] target/riscv: add zvkg cpu property,
Lawrence Hunter <=
- [PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv, Lawrence Hunter, 2023/02/02
- [PATCH 38/39] target/riscv: Add Zvksed support, Lawrence Hunter, 2023/02/02
- [PATCH 30/39] target/riscv: Add vsm3c.vi decoding, translation and execution support, Lawrence Hunter, 2023/02/02