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[PATCH 01/39] target/riscv: add zvkb cpu property
From: |
Lawrence Hunter |
Subject: |
[PATCH 01/39] target/riscv: add zvkb cpu property |
Date: |
Thu, 2 Feb 2023 12:41:52 +0000 |
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---
target/riscv/cpu.c | 12 ++++++++++++
target/riscv/cpu.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc75ca7667..bd34119c75 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -100,6 +100,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
+ ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
@@ -792,6 +793,17 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ /*
+ * In principle zve*{x,d} would also suffice here, were they supported
+ * in qemu
+ */
+ if (cpu->cfg.ext_zvkb &&
+ !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v)) {
+ error_setg(
+ errp, "Vector crypto extensions require V or Zve* extensions");
+ return;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
cpu->cfg.ext_zhinxmin) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f5609b62a2..d4824ad0bb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -461,6 +461,7 @@ struct RISCVCPUConfig {
bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve64f;
+ bool ext_zvkb;
bool ext_zmmul;
bool ext_smaia;
bool ext_ssaia;
--
2.39.1
- [PATCH 00/39] Add RISC-V vector cryptography extensions, Lawrence Hunter, 2023/02/02
- [PATCH 07/39] target/riscv: Add vbrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 01/39] target/riscv: add zvkb cpu property,
Lawrence Hunter <=
- [PATCH 08/39] target/riscv: Add vrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 05/39] target/riscv: Add vclmulh.vx decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 17/39] target/riscv: Add vaesdm.vs decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 27/39] target/riscv: expose zvknh cpu properties, Lawrence Hunter, 2023/02/02
- [PATCH 15/39] target/riscv: Add vaesdf.vs decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 23/39] target/riscv: expose zvkns cpu property, Lawrence Hunter, 2023/02/02
- [PATCH 04/39] target/riscv: Add vclmulh.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02