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[PATCH v4 3/9] igb: add ICR_RXDW
From: |
Sriram Yagnaraman |
Subject: |
[PATCH v4 3/9] igb: add ICR_RXDW |
Date: |
Wed, 1 Feb 2023 12:17:16 +0100 |
IGB uses RXDW ICR bit to indicate that rx descriptor has been written
back. This is the same as RXT0 bit in older HW.
Signed-off-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
---
hw/net/e1000x_regs.h | 4 ++++
hw/net/igb_core.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h
index fb5b861135..f509db73a7 100644
--- a/hw/net/e1000x_regs.h
+++ b/hw/net/e1000x_regs.h
@@ -335,6 +335,7 @@
#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
#define E1000_ICR_RXO 0x00000040 /* rx overrun */
#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
+#define E1000_ICR_RXDW 0x00000080 /* rx desc written back */
#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
@@ -378,6 +379,7 @@
#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -407,6 +409,7 @@
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -441,6 +444,7 @@
#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index b484e6ac30..1ddf54f630 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1582,7 +1582,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
n |= E1000_ICS_RXDMT0;
}
- n |= E1000_ICR_RXT0;
+ n |= E1000_ICR_RXDW;
trace_e1000e_rx_written_to_guest(rxr.i->idx);
}
--
2.34.1
- [PATCH v4 0/9] igb: merge changes from <address@hidden>, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 6/9] igb: respect E1000_VMOLR_RSSE, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 7/9] igb: implement VF Tx and Rx stats, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 4/9] igb: implement VFRE and VFTE registers, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 1/9] MAINTAINERS: Add Sriram Yagnaraman as a igb reviewer, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 5/9] igb: check oversized packets for VMDq, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 8/9] igb: respect VT_CTL ignore MAC field, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 9/9] igb: respect VMVIR and VMOLR for VLAN, Sriram Yagnaraman, 2023/02/01
- [PATCH v4 3/9] igb: add ICR_RXDW,
Sriram Yagnaraman <=
- [PATCH v4 2/9] igb: handle PF/VF reset properly, Sriram Yagnaraman, 2023/02/01