[PATCH] target/riscv: Add RVV registers to log

[Ivan Klokov]

Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular regs.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
---
 accel/tcg/cpu-exec.c  |  5 +++++
 include/hw/core/cpu.h |  2 ++
 include/qemu/log.h    |  3 ++-
 target/riscv/cpu.c    | 49 ++++++++++++++++++++++++++++++++++++++++++-
 util/log.c            |  3 +++
 5 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 04cd1f3092..90e3b79544 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -296,6 +296,11 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu,
                 }
 #if defined(TARGET_I386)
                 flags |= CPU_DUMP_CCOP;
+#endif
+#if defined(TARGET_RISCV)
+                if (qemu_loglevel_mask(CPU_LOG_RISCV_RVV)) {
+                    flags |= CPU_DUMP_RVV;
+                }
 #endif
                 cpu_dump_state(cpu, logfile, flags);
                 qemu_log_unlock(logfile);
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2417597236..82d90854c5 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -543,11 +543,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
  * @CPU_DUMP_CODE:
  * @CPU_DUMP_FPU: dump FPU register state, not just integer
  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
+ * @CPU_DUMP_RVV: dump RISC-V RVV registers
  */
 enum CPUDumpFlags {
     CPU_DUMP_CODE = 0x00010000,
     CPU_DUMP_FPU  = 0x00020000,
     CPU_DUMP_CCOP = 0x00040000,
+    CPU_DUMP_RVV  = 0x00080000,
 };
 
 /**
diff --git a/include/qemu/log.h b/include/qemu/log.h
index c5643d8dd5..fb061d75f8 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -35,7 +35,8 @@ bool qemu_log_separate(void);
 /* LOG_STRACE is used for user-mode strace logging. */
 #define LOG_STRACE         (1 << 19)
 #define LOG_PER_THREAD     (1 << 20)
-
+/* RISC-V "V" Vector Extension */
+#define CPU_LOG_RISCV_RVV  (1 << 21)
 /* Lock/unlock output. */
 
 FILE *qemu_log_trylock(void) G_GNUC_WARN_UNUSED_RESULT;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 14a7027095..319aac5517 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -154,6 +154,14 @@ const char * const riscv_fpr_regnames[] = {
   "f30/ft10", "f31/ft11"
 };
 
+const char * const riscv_rvv_regnames[] = {
+  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
+  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
+  "v14", "v15", "v16", "v17", "v18", "v19", "v20",
+  "v21", "v22", "v23", "v24", "v25", "v26", "v27",
+  "v28", "v29", "v30", "v31"
+};
+
 static const char * const riscv_excp_names[] = {
     "misaligned_fetch",
     "fault_fetch",
@@ -375,7 +383,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int 
flags)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    int i;
+    int i, j;
+    uint8_t *p;
 
 #if !defined(CONFIG_USER_ONLY)
     if (riscv_has_ext(env, RVH)) {
@@ -459,6 +468,44 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, 
int flags)
             }
         }
     }
+    if (riscv_has_ext(env, RVV)) {
+        if (flags & CPU_DUMP_RVV) {
+
+            static const int dump_rvv_csrs[] = {
+                        CSR_VSTART,
+                        CSR_VXSAT,
+                        CSR_VXRM,
+                        CSR_VCSR,
+                        CSR_VL,
+                        CSR_VTYPE,
+                        CSR_VLENB,
+                    };
+            for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
+                int csrno = dump_rvv_csrs[i];
+                target_ulong val = 0;
+                RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+                /*
+                 * Rely on the smode, hmode, etc, predicates within csr.c
+                 * to do the filtering of the registers that are present.
+                 */
+                if (res == RISCV_EXCP_NONE) {
+                    qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                                 csr_ops[csrno].name, val);
+                }
+            }
+            uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+
+            for (i = 0; i < 32; i++) {
+                qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
+                p = (uint8_t *)env->vreg;
+                for (j = 0; j < vlenb; j++) {
+                    qemu_fprintf(f, "%02x", *(p + i * vlenb + j));
+                }
+                qemu_fprintf(f, "\n");
+            }
+        }
+    }
 }
 
 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
diff --git a/util/log.c b/util/log.c
index 7837ff9917..8827109b5c 100644
--- a/util/log.c
+++ b/util/log.c
@@ -495,6 +495,9 @@ const QEMULogItem qemu_log_items[] = {
       "log every user-mode syscall, its input, and its result" },
     { LOG_PER_THREAD, "tid",
       "open a separate log file per thread; filename must contain '%d'" },
+    { CPU_LOG_RISCV_RVV, "rvv",
+      "RISC-V only: add RISC-V \"V\" Vector Extension registers "
+            "in the 'cpu' logging" },
     { 0, NULL, NULL },
 };
 
-- 
2.34.1