[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/34] hw/timer/imx_epit: hard reset initializes CR with 0
From: |
Peter Maydell |
Subject: |
[PULL 14/34] hw/timer/imx_epit: hard reset initializes CR with 0 |
Date: |
Thu, 5 Jan 2023 16:43:57 +0000 |
From: Axel Heider <axel.heider@hensoldt.net>
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/imx_epit.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 7af3a8b10e8..39f47222d05 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -99,12 +99,14 @@ static void imx_epit_set_freq(IMXEPITState *s)
/*
* This is called both on hardware (device) reset and software reset.
*/
-static void imx_epit_reset(DeviceState *dev)
+static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
{
- IMXEPITState *s = IMX_EPIT(dev);
-
/* Soft reset doesn't touch some bits; hard reset clears them */
- s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
+ if (is_hard_reset) {
+ s->cr = 0;
+ } else {
+ s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
+ }
s->sr = 0;
s->lr = EPIT_TIMER_MAX;
s->cmp = 0;
@@ -205,7 +207,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,
uint64_t value,
s->cr = value & 0x03ffffff;
if (s->cr & CR_SWR) {
/* handle the reset */
- imx_epit_reset(DEVICE(s));
+ imx_epit_reset(s, false);
}
/*
@@ -377,12 +379,18 @@ static void imx_epit_realize(DeviceState *dev, Error
**errp)
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
}
+static void imx_epit_dev_reset(DeviceState *dev)
+{
+ IMXEPITState *s = IMX_EPIT(dev);
+ imx_epit_reset(s, true);
+}
+
static void imx_epit_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = imx_epit_realize;
- dc->reset = imx_epit_reset;
+ dc->reset = imx_epit_dev_reset;
dc->vmsd = &vmstate_imx_timer_epit;
dc->desc = "i.MX periodic timer";
}
--
2.25.1
- [PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, (continued)
- [PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, Peter Maydell, 2023/01/05
- [PULL 08/34] target/arm: Add ARM Cortex-R52 CPU, Peter Maydell, 2023/01/05
- [PULL 07/34] target/arm: Add PMSAv8r functionality, Peter Maydell, 2023/01/05
- [PULL 12/34] hw/timer/imx_epit: define SR_OCIF, Peter Maydell, 2023/01/05
- [PULL 10/34] hw/timer/imx_epit: improve comments, Peter Maydell, 2023/01/05
- [PULL 13/34] hw/timer/imx_epit: update interrupt state on CR write access, Peter Maydell, 2023/01/05
- [PULL 09/34] target/arm: fix handling of HLT semihosting in system mode, Peter Maydell, 2023/01/05
- [PULL 06/34] target/arm: Add PMSAv8r registers, Peter Maydell, 2023/01/05
- [PULL 16/34] hw/timer/imx_epit: remove explicit fields cnt and freq, Peter Maydell, 2023/01/05
- [PULL 17/34] hw/timer/imx_epit: fix compare timer handling, Peter Maydell, 2023/01/05
- [PULL 14/34] hw/timer/imx_epit: hard reset initializes CR with 0,
Peter Maydell <=
- [PULL 19/34] target/arm: Fix checkpatch space errors in helper.c, Peter Maydell, 2023/01/05
- [PULL 24/34] hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg, Peter Maydell, 2023/01/05
- [PULL 25/34] hw/arm/nseries: Constify various read-only arrays, Peter Maydell, 2023/01/05
- [PULL 23/34] target/arm: cleanup cpu includes, Peter Maydell, 2023/01/05
- [PULL 15/34] hw/timer/imx_epit: factor out register write handlers, Peter Maydell, 2023/01/05
- [PULL 21/34] target/arm: Remove unused includes from m_helper.c, Peter Maydell, 2023/01/05
- [PULL 22/34] target/arm: Remove unused includes from helper.c, Peter Maydell, 2023/01/05
- [PULL 20/34] target/arm: Fix checkpatch brace errors in helper.c, Peter Maydell, 2023/01/05
- [PULL 27/34] target/arm: align exposed ID registers with Linux, Peter Maydell, 2023/01/05
- [PULL 26/34] hw/arm/nseries: Silent -Wmissing-field-initializers warning, Peter Maydell, 2023/01/05