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[PATCH v5 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
From: |
tobias.roehmel |
Subject: |
[PATCH v5 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 |
Date: |
Sun, 27 Nov 2022 14:21:09 +0100 |
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
---
target/arm/debug_helper.c | 3 +++
target/arm/internals.h | 4 ++++
target/arm/tlb_helper.c | 4 ++++
3 files changed, 11 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index c21739242c..2f6ddc0da5 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -437,6 +437,9 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
using_lpae = true;
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ using_lpae = true;
} else {
if (arm_feature(env, ARM_FEATURE_LPAE) &&
(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
diff --git a/target/arm/internals.h b/target/arm/internals.h
index d9121d9ff8..1dfc593f28 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -253,6 +253,10 @@ unsigned int arm_pamax(ARMCPU *cpu);
static inline bool extended_addresses_enabled(CPUARMState *env)
{
uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ return true;
+ }
return arm_el_is_aa64(env, 1) ||
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
}
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 0f4f4fc809..60abcbebe6 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -19,6 +19,10 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx
mmu_idx)
if (el == 2 || arm_el_is_aa64(env, el)) {
return true;
}
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ return true;
+ }
if (arm_feature(env, ARM_FEATURE_LPAE)
&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
return true;
--
2.34.1
- [PATCH v5 0/7] Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/11/27
- [PATCH v5 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs, tobias.roehmel, 2022/11/27
- [PATCH v5 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA, tobias.roehmel, 2022/11/27
- [PATCH v5 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32,
tobias.roehmel <=
- [PATCH v5 6/7] target/arm: Add PMSAv8r functionality, tobias.roehmel, 2022/11/27
- [PATCH v5 7/7] target/arm: Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/11/27
- [PATCH v5 3/7] target/arm: Make stage_2_format for cache attributes optional, tobias.roehmel, 2022/11/27
- [PATCH v5 5/7] target/arm: Add PMSAv8r registers, tobias.roehmel, 2022/11/27
- Re: [PATCH v5 0/7] Add ARM Cortex-R52 CPU, Peter Maydell, 2022/11/29