qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 4/4] be less conservative with the 64bit pci io window


From: Kevin O'Connor
Subject: Re: [PATCH 4/4] be less conservative with the 64bit pci io window
Date: Tue, 22 Nov 2022 13:43:16 -0500

On Mon, Nov 21, 2022 at 11:32:13AM +0100, Gerd Hoffmann wrote:
> Current seabios code will only enable and use the 64bit pci io window in
> case it runs out of space in the 32bit pci mmio window below 4G.
> 
> This patch will also enable the 64bit pci io window when
>   (a) RAM above 4G is present, and
>   (b) the physical address space size is known, and
>   (c) seabios is running on a 64bit capable processor.
> 
> This operates with the assumption that guests which are ok with memory
> above 4G most likely can handle mmio above 4G too.

Thanks.  In general, the series looks good to me.  Can you elaborate
on the background to this change though?  It sounds like there is a
(small) risk of a regression, so I think it would be good to have a
high level understanding of what is driving this memory reorg.

Cheers,
-Kevin


> 
> In case the 64bit pci io window is enabled also assign more memory to
> prefetchable pci bridge windows (scale with address space).
> 
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
>  src/fw/pciinit.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
> index ad6def93633b..3e9636b139a4 100644
> --- a/src/fw/pciinit.c
> +++ b/src/fw/pciinit.c
> @@ -51,6 +51,7 @@ u64 pcimem_end     = BUILD_PCIMEM_END;
>  u64 pcimem64_start = BUILD_PCIMEM64_START;
>  u64 pcimem64_end   = BUILD_PCIMEM64_END;
>  u64 pci_io_low_end = 0xa000;
> +u32 pci_use_64bit  = 0;
>  
>  struct pci_region_entry {
>      struct pci_device *dev;
> @@ -920,6 +921,8 @@ static int pci_bios_check_devices(struct pci_bus *busses)
>          for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
>              u64 align = (type == PCI_REGION_TYPE_IO) ?
>                  PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
> +            if (pci_use_64bit && (type == PCI_REGION_TYPE_PREFMEM))
> +                align = (u64)1 << (PhysBits - 11);
>              if (!pci_bridge_has_region(s->bus_dev, type))
>                  continue;
>              u64 size = 0;
> @@ -1108,7 +1111,7 @@ static void pci_bios_map_devices(struct pci_bus *busses)
>          panic("PCI: out of I/O address space\n");
>  
>      dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
> -    if (pci_bios_init_root_regions_mem(busses)) {
> +    if (pci_use_64bit || pci_bios_init_root_regions_mem(busses)) {
>          struct pci_region r64_mem, r64_pref;
>          r64_mem.list.first = NULL;
>          r64_pref.list.first = NULL;
> @@ -1174,6 +1177,9 @@ pci_setup(void)
>  
>      dprintf(3, "pci setup\n");
>  
> +    if (PhysBits >= 36 && LongMode && RamSizeOver4G)
> +        pci_use_64bit = 1;
> +
>      dprintf(1, "=== PCI bus & bridge init ===\n");
>      if (pci_probe_host() != 0) {
>          return;
> -- 
> 2.38.1
> 
> 



reply via email to

[Prev in Thread] Current Thread [Next in Thread]