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[PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/
From: |
Alex Bennée |
Subject: |
[PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ |
Date: |
Fri, 11 Nov 2022 18:25:15 +0000 |
Hi,
This series attempts to improve the modelling of non-CPU writes to
peripherals by expanding the MemTxAttrs to carry more details about
the requester. There are only 3 requester types, the CPU, the PCI bus
and the MACHINE. The last is intended for machine specific buses and
leaves the details of how to decode that information to machine
specific code.
I've extended this beyond just being an Arm only experiment and into
some other machine types. Perhaps the most complicated bit was
tweaking the modelling of the IOAPIC/APIC which gave me the first use
of MTRT_MACHINE (although we don't fully validate the source we do now
correctly drop CPU accesses to the APIC MSI region).
The longer term goal will be to eliminate all the legacy mem
read/write functions and use MemTxAttrs everywhere.
The final patch deprecates the use of current_cpu in hw/ for new code
as a comment. What do people think?
Based-on: 20221111145529.4020801-1-alex.bennee@linaro.org
Alex Bennée (20):
hw: encode accessing CPU index in MemTxAttrs
target/arm: ensure TCG IO accesses set appropriate MemTxAttrs
target/arm: ensure HVF traps set appropriate MemTxAttrs
target/arm: ensure KVM traps set appropriate MemTxAttrs
target/arm: ensure m-profile helpers set appropriate MemTxAttrs
qtest: make read/write operation appear to be from CPU
hw/intc/gic: use MxTxAttrs to divine accessing CPU
hw/timer: convert mptimer access to attrs to derive cpu index
hw/arm: remove current_cpu hack from pxa2xx access
target/microblaze: initialise MemTxAttrs for CPU access
target/sparc: initialise MemTxAttrs for CPU access
target/riscv: initialise MemTxAttrs for CPU access
target/i386: add explicit initialisation for MexTxAttrs
hw/audio: explicitly set .requester_type for intel-hda
hw/i386: update vapic_write to use MemTxAttrs
include: add MEMTXATTRS_MACHINE helper
hw/intc: properly model IOAPIC MSI messages
hw/i386: convert apic access to use MemTxAttrs
hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb
include/hw: add commentary to current_cpu export
include/exec/memattrs.h | 76 +++++++++++---
include/hw/core/cpu.h | 14 +++
include/hw/i386/apic.h | 2 +-
include/hw/i386/ioapic_internal.h | 2 +
include/hw/isa/apm.h | 2 +-
target/i386/cpu.h | 4 +-
hw/acpi/ich9.c | 1 -
hw/acpi/piix4.c | 2 +-
hw/arm/pxa2xx.c | 2 +-
hw/audio/intel-hda.c | 2 +-
hw/i386/amd_iommu.c | 6 +-
hw/i386/intel_iommu.c | 2 +-
hw/i386/kvmvapic.c | 19 ++--
hw/i386/x86.c | 11 +--
hw/intc/apic.c | 62 ++++++++----
hw/intc/arm_gic.c | 159 +++++++++++++++++++-----------
hw/intc/ioapic.c | 35 +++++--
hw/isa/apm.c | 21 +++-
hw/isa/lpc_ich9.c | 5 +-
hw/misc/tz-mpc.c | 2 +-
hw/misc/tz-msc.c | 6 +-
hw/pci/pci.c | 4 +-
hw/timer/arm_mptimer.c | 49 ++++++---
softmmu/qtest.c | 26 ++---
target/arm/hvf/hvf.c | 4 +-
target/arm/kvm.c | 9 +-
target/arm/m_helper.c | 12 +--
target/arm/ptw.c | 3 +-
target/arm/tlb_helper.c | 2 +-
target/i386/hax/hax-all.c | 2 +-
target/i386/nvmm/nvmm-all.c | 2 +-
target/i386/sev.c | 2 +-
target/i386/whpx/whpx-all.c | 2 +-
target/microblaze/helper.c | 4 +-
target/riscv/cpu_helper.c | 2 +-
target/sparc/mmu_helper.c | 6 +-
36 files changed, 370 insertions(+), 194 deletions(-)
--
2.34.1
- [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/,
Alex Bennée <=
- [PATCH v5 03/20] target/arm: ensure HVF traps set appropriate MemTxAttrs, Alex Bennée, 2022/11/11
- [PATCH v5 04/20] target/arm: ensure KVM traps set appropriate MemTxAttrs, Alex Bennée, 2022/11/11
- [PATCH v5 05/20] target/arm: ensure m-profile helpers set appropriate MemTxAttrs, Alex Bennée, 2022/11/11
- [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index, Alex Bennée, 2022/11/11
- [PATCH v5 07/20] hw/intc/gic: use MxTxAttrs to divine accessing CPU, Alex Bennée, 2022/11/11
- [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages, Alex Bennée, 2022/11/11
- [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs, Alex Bennée, 2022/11/11