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[PATCH for-8.0 v3 08/45] target/sparc: Avoid TCGV_{LOW,HIGH}
From: |
Richard Henderson |
Subject: |
[PATCH for-8.0 v3 08/45] target/sparc: Avoid TCGV_{LOW,HIGH} |
Date: |
Fri, 11 Nov 2022 17:40:24 +1000 |
Use the official extend/extract functions instead of routines
that will shortly be internal to tcg.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 21 ++++-----------------
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 34858eb95f..150aeecd14 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -163,13 +163,6 @@ static inline void gen_update_fprs_dirty(DisasContext *dc,
int rd)
/* floating point registers moves */
static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
{
-#if TCG_TARGET_REG_BITS == 32
- if (src & 1) {
- return TCGV_LOW(cpu_fpr[src / 2]);
- } else {
- return TCGV_HIGH(cpu_fpr[src / 2]);
- }
-#else
TCGv_i32 ret = get_temp_i32(dc);
if (src & 1) {
tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
@@ -177,22 +170,16 @@ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned
int src)
tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
}
return ret;
-#endif
}
static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
{
-#if TCG_TARGET_REG_BITS == 32
- if (dst & 1) {
- tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
- } else {
- tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
- }
-#else
- TCGv_i64 t = (TCGv_i64)v;
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t, v);
tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
(dst & 1 ? 0 : 32), 32);
-#endif
+ tcg_temp_free_i64(t);
gen_update_fprs_dirty(dc, dst);
}
--
2.34.1
- [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 01/45] meson: Move CONFIG_TCG_INTERPRETER to config_host, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 02/45] tcg: Tidy tcg_reg_alloc_op, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 03/45] tcg: Introduce paired register allocation, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 04/45] tcg/s390x: Use register pair allocation for div and mulu2, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 05/45] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 06/45] tcg: Remove TCG_TARGET_STACK_GROWSUP, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 08/45] target/sparc: Avoid TCGV_{LOW,HIGH},
Richard Henderson <=
- [PATCH for-8.0 v3 07/45] accel/tcg: Set cflags_next_tb in cpu_common_initfn, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 09/45] tcg: Move TCG_{LOW,HIGH} to tcg-internal.h, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 11/45] tcg: Simplify calls to temp_sync vs mem_coherent, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 10/45] tcg: Add temp_subindex to TCGTemp, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 12/45] tcg: Allocate TCGTemp pairs in host memory order, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 13/45] tcg: Move TCG_TYPE_COUNT outside enum, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 15/45] tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind, Richard Henderson, 2022/11/11
- [PATCH for-8.0 v3 16/45] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64, Richard Henderson, 2022/11/11