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[PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting
From: |
Peter Maydell |
Subject: |
[PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel |
Date: |
Fri, 4 Nov 2022 11:35:09 +0000 |
When we direct boot a kernel on a CPU which emulates EL3, we need
to set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
For SVE and SME this includes:
- ZCR_EL3.LEN must be initialised to the same value for all CPUs the
kernel is executed on.
- SMCR_EL3.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
Although we are technically compliant with this, the "same value" we
currently use by default is the reset value of 0. This will end up
forcing the guest kernel's SVE and SME vector length to be only the
smallest supported length.
Initialize the vector length fields to their maximum possible value,
which is 0xf. If the implementation doesn't actually support that
vector length then the effective vector length will be constrained
down to the maximum supported value at point of use.
This allows the guest to use all the vector lengths the emulated CPU
supports (by programming the _EL2 and _EL1 versions of these
registers.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-2-peter.maydell@linaro.org
---
hw/arm/boot.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index b106f314685..17d38260faf 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -764,10 +764,12 @@ static void do_cpu_reset(void *opaque)
}
if (cpu_isar_feature(aa64_sve, cpu)) {
env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
+ env->vfp.zcr_el[3] = 0xf;
}
if (cpu_isar_feature(aa64_sme, cpu)) {
env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
env->cp15.scr_el3 |= SCR_ENTP2;
+ env->vfp.smcr_el[3] = 0xf;
}
/* AArch64 kernels never boot in secure mode */
assert(!info->secure_boot);
--
2.25.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2022/11/04
- [PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel,
Peter Maydell <=
- [PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel, Peter Maydell, 2022/11/04
- [PULL 3/7] target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB, Peter Maydell, 2022/11/04
- [PULL 6/7] target/arm: Honor HCR_E2H and HCR_TGE in ats_write64(), Peter Maydell, 2022/11/04
- [PULL 4/7] target/arm: Fix Privileged Access Never (PAN) for aarch32, Peter Maydell, 2022/11/04
- [PULL 5/7] target/arm: Copy the entire vector in DO_ZIP, Peter Maydell, 2022/11/04
- [PULL 7/7] target/arm: Two fixes for secure ptw, Peter Maydell, 2022/11/04
- Re: [PULL 0/7] target-arm queue, Stefan Hajnoczi, 2022/11/07