Re: [PATCH RFC] target/loongarch: Fix emulation of float-point disable exception

[Richard Henderson]

On 11/3/22 19:02, Rui Wang wrote:
> +static void check_fpe(DisasContext *ctx)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    TCGLabel *skip = gen_new_label();
> +    TCGv tmp = tcg_temp_new();
> +
> +    tcg_gen_andi_tl(tmp, cpu_euen, R_CSR_EUEN_FPE_MASK);
> +    tcg_gen_brcond_tl(TCG_COND_NE, tmp, ctx->zero, skip);
> +    tcg_temp_free(tmp);
> +
> +    generate_exception(ctx, EXCCODE_FPD);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> +
> +    gen_set_label(skip);
> +#endif
> +}

While this works, it is very inefficient.

You should cache the state of this bit in tb->flags, as set by 
cpu_get_tb_cpu_state.
Compare, for instance, target/riscv/,

FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)

for which ctx->mstatus_hs_fs controls whether the fpu is clean, dirty, or 
disabled.

At present, loongarch is using 3 bits of tb->flags for the mmu_idx, re-using that for 
privilege level in check_plv.  Which is nearly correct, except for the case of paging 
disabled in user mode.  This probably never happens in practice, but unless the cpu 
disallows such a state, this should be corrected.


r~