[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 5/6] i386: Initialize AMX CPUID leaves with corresponding env-
From: |
Wang, Lei |
Subject: |
[PATCH v2 5/6] i386: Initialize AMX CPUID leaves with corresponding env->features[] leaves |
Date: |
Wed, 2 Nov 2022 01:52:55 -0700 |
The AMX-related CPUID value, i.e., CPUID(0x1D,1):EAX, CPUID(0x1D,1):EBX,
CPUID(0x1D,1):ECX and CPUID(0x1E,0):EBX are hard-coded to Sapphire Rapids
without considering future platforms.
Replace these hard-coded values with env->features[], so QEMU can pass the
right value to KVM.
Signed-off-by: Wang, Lei <lei4.wang@intel.com>
---
target/i386/cpu.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 53223857ba..fce5a04be7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -576,16 +576,16 @@ static CPUCacheInfo legacy_l3_cache = {
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support
2K,4K,8K,16K,32K,64K */
/* CPUID Leaf 0x1D constants: */
-#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
-#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
-#define INTEL_AMX_BYTES_PER_TILE 0x400
-#define INTEL_AMX_BYTES_PER_ROW 0x40
-#define INTEL_AMX_TILE_MAX_NAMES 0x8
-#define INTEL_AMX_TILE_MAX_ROWS 0x10
+#define INTEL_SPR_AMX_TILE_MAX_SUBLEAF 0x1
+#define INTEL_SPR_AMX_TOTAL_TILE_BYTES 0x2000
+#define INTEL_SPR_AMX_BYTES_PER_TILE 0x400
+#define INTEL_SPR_AMX_BYTES_PER_ROW 0x40
+#define INTEL_SPR_AMX_TILE_MAX_NAMES 0x8
+#define INTEL_SPR_AMX_TILE_MAX_ROWS 0x10
/* CPUID Leaf 0x1E constants: */
-#define INTEL_AMX_TMUL_MAX_K 0x10
-#define INTEL_AMX_TMUL_MAX_N 0x40
+#define INTEL_SPR_AMX_TMUL_MAX_K 0x10
+#define INTEL_SPR_AMX_TMUL_MAX_N 0x40
void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
@@ -5765,12 +5765,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
if (count == 0) {
/* Highest numbered palette subleaf */
- *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
+ *eax = INTEL_SPR_AMX_TILE_MAX_SUBLEAF;
} else if (count == 1) {
- *eax = INTEL_AMX_TOTAL_TILE_BYTES |
- (INTEL_AMX_BYTES_PER_TILE << 16);
- *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
- *ecx = INTEL_AMX_TILE_MAX_ROWS;
+ *eax = env->features[FEAT_1D_1_EAX];
+ *ebx = env->features[FEAT_1D_1_EBX];
+ *ecx = env->features[FEAT_1D_1_ECX];
}
break;
}
@@ -5786,7 +5785,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
if (count == 0) {
/* Highest numbered palette subleaf */
- *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
+ *ebx = env->features[FEAT_1E_0_EBX];
}
break;
}
--
2.34.1
- [PATCH v2 0/6] Support for new CPU model SapphireRapids, Wang, Lei, 2022/11/02
- [PATCH v2 1/6] i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E, Wang, Lei, 2022/11/02
- [PATCH v2 3/6] i386: Introduce new struct "MultiBitFeatureInfo" for multi-bit features, Wang, Lei, 2022/11/02
- [PATCH v2 5/6] i386: Initialize AMX CPUID leaves with corresponding env->features[] leaves,
Wang, Lei <=
- [PATCH v2 2/6] i386: Remove unused parameter "uint32_t bit" in feature_word_description(), Wang, Lei, 2022/11/02
- [PATCH v2 4/6] i386: Mask and report unavailable multi-bit feature values, Wang, Lei, 2022/11/02
- [PATCH v2 6/6] i386: Add new CPU model SapphireRapids, Wang, Lei, 2022/11/02