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[PULL 20/62] target/ppc: always use ppc_set_irq to set env->pending_inte
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 20/62] target/ppc: always use ppc_set_irq to set env->pending_interrupts |
Date: |
Fri, 28 Oct 2022 13:39:09 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Use ppc_set_irq to raise/clear interrupts to ensure CPU_INTERRUPT_HARD
will be set/reset accordingly.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20221011204829.1641124-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/excp_helper.c | 17 +++++++----------
target/ppc/misc_helper.c | 9 ++-------
2 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d168789fc0..37d352619b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "internal.h"
#include "helper_regs.h"
+#include "hw/ppc/ppc.h"
#include "trace.h"
@@ -2086,7 +2087,6 @@ void helper_rfebb(CPUPPCState *env, target_ulong s)
static void do_ebb(CPUPPCState *env, int ebb_excp)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
/*
* FSCR_EBB and FSCR_IC_EBB are the same bits used with
@@ -2104,8 +2104,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp)
if (FIELD_EX64(env->msr, MSR, PR)) {
powerpc_excp(cpu, ebb_excp);
} else {
- env->pending_interrupts |= PPC_INTERRUPT_EBB;
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ ppc_set_irq(cpu, PPC_INTERRUPT_EBB, 1);
}
}
@@ -2298,7 +2297,7 @@ void helper_msgclr(CPUPPCState *env, target_ulong rb)
return;
}
- env->pending_interrupts &= ~irq;
+ ppc_set_irq(env_archcpu(env), irq, 0);
}
void helper_msgsnd(target_ulong rb)
@@ -2317,8 +2316,7 @@ void helper_msgsnd(target_ulong rb)
CPUPPCState *cenv = &cpu->env;
if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
- cenv->pending_interrupts |= irq;
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ ppc_set_irq(cpu, irq, 1);
}
}
qemu_mutex_unlock_iothread();
@@ -2342,7 +2340,7 @@ void helper_book3s_msgclr(CPUPPCState *env, target_ulong
rb)
return;
}
- env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL;
+ ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0);
}
static void book3s_msgsnd_common(int pir, int irq)
@@ -2356,8 +2354,7 @@ static void book3s_msgsnd_common(int pir, int irq)
/* TODO: broadcast message to all threads of the same processor */
if (cenv->spr_cb[SPR_PIR].default_value == pir) {
- cenv->pending_interrupts |= irq;
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ ppc_set_irq(cpu, irq, 1);
}
}
qemu_mutex_unlock_iothread();
@@ -2383,7 +2380,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong
rb)
return;
}
- env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL;
+ ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0);
}
/*
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 05e35572bc..a9bc1522e2 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -25,6 +25,7 @@
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "mmu-book3s-v3.h"
+#include "hw/ppc/ppc.h"
#include "helper_regs.h"
@@ -173,7 +174,6 @@ target_ulong helper_load_dpdes(CPUPPCState *env)
void helper_store_dpdes(CPUPPCState *env, target_ulong val)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
@@ -184,12 +184,7 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val)
return;
}
- if (val & 0x1) {
- env->pending_interrupts |= PPC_INTERRUPT_DOORBELL;
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- } else {
- env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL;
- }
+ ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1);
}
#endif /* defined(TARGET_PPC64) */
--
2.37.3
- [PULL 06/62] target/ppc: move msgsync to decodetree, (continued)
- [PULL 06/62] target/ppc: move msgsync to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 08/62] target/ppc: Move VMH[R]ADDSHS instruction to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 09/62] target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 13/62] target/ppc: Move VABSDU[BHW] to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 17/62] target/ppc: Moved XSTSTDC[QDS]P to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 10/62] target/ppc: Move VNEG[WD] to decodtree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 15/62] target/ppc: Use gvec to decode XVCPSGN[SD]P, Daniel Henrique Barboza, 2022/10/28
- [PULL 18/62] target/ppc: Use gvec to decode XVTSTDC[DS]P, Daniel Henrique Barboza, 2022/10/28
- [PULL 19/62] target/ppc: define PPC_INTERRUPT_* values directly, Daniel Henrique Barboza, 2022/10/28
- [PULL 16/62] target/ppc: Moved XVTSTDC[DS]P to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 20/62] target/ppc: always use ppc_set_irq to set env->pending_interrupts,
Daniel Henrique Barboza <=
- [PULL 21/62] target/ppc: split interrupt masking and delivery from ppc_hw_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 12/62] target/ppc: Move VAVG[SU][BHW] to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 22/62] target/ppc: prepare to split interrupt masking and delivery by excp_model, Daniel Henrique Barboza, 2022/10/28
- [PULL 14/62] target/ppc: Use gvec to decode XV[N]ABS[DS]P/XVNEG[DS]P, Daniel Henrique Barboza, 2022/10/28
- [PULL 11/62] target/ppc: Move VPRTYB[WDQ] to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 23/62] target/ppc: create an interrupt masking method for POWER9/POWER10, Daniel Henrique Barboza, 2022/10/28
- [PULL 24/62] target/ppc: remove unused interrupts from p9_next_unmasked_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 26/62] target/ppc: remove unused interrupts from p9_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 25/62] target/ppc: create an interrupt deliver method for POWER9/POWER10, Daniel Henrique Barboza, 2022/10/28
- [PULL 27/62] target/ppc: remove generic architecture checks from p9_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28