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[PATCH v4 09/17] hw/pci/pci_bridge: Omit errp for pci_add_capability
From: |
Akihiko Odaki |
Subject: |
[PATCH v4 09/17] hw/pci/pci_bridge: Omit errp for pci_add_capability |
Date: |
Thu, 27 Oct 2022 15:36:57 +0900 |
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
hw/pci-bridge/i82801b11.c | 14 ++------------
hw/pci-bridge/pcie_root_port.c | 7 +------
hw/pci-bridge/xio3130_downstream.c | 8 ++------
hw/pci-bridge/xio3130_upstream.c | 8 ++------
hw/pci/pci_bridge.c | 21 ++++++---------------
include/hw/pci/pci_bridge.h | 5 ++---
6 files changed, 15 insertions(+), 48 deletions(-)
diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
index f28181e210..f45dcdbacc 100644
--- a/hw/pci-bridge/i82801b11.c
+++ b/hw/pci-bridge/i82801b11.c
@@ -61,21 +61,11 @@ typedef struct I82801b11Bridge {
static void i82801b11_bridge_realize(PCIDevice *d, Error **errp)
{
- int rc;
-
pci_bridge_initfn(d, TYPE_PCI_BUS);
- rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
- I82801ba_SSVID_SVID, I82801ba_SSVID_SSID,
- errp);
- if (rc < 0) {
- goto err_bridge;
- }
+ pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
+ I82801ba_SSVID_SVID, I82801ba_SSVID_SSID);
pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB);
- return;
-
-err_bridge:
- pci_bridge_exitfn(d);
}
static const VMStateDescription i82801b11_bridge_dev_vmstate = {
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
index 460e48269d..a9d8c2adb4 100644
--- a/hw/pci-bridge/pcie_root_port.c
+++ b/hw/pci-bridge/pcie_root_port.c
@@ -74,12 +74,7 @@ static void rp_realize(PCIDevice *d, Error **errp)
}
pcie_port_init_reg(d);
- rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,
- rpc->ssid, errp);
- if (rc < 0) {
- error_append_hint(errp, "Can't init SSV ID, error %d\n", rc);
- goto err_bridge;
- }
+ pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid);
if (rpc->interrupts_init) {
rc = rpc->interrupts_init(d, errp);
diff --git a/hw/pci-bridge/xio3130_downstream.c
b/hw/pci-bridge/xio3130_downstream.c
index 05e2b06c0c..eea3d3a2df 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -81,12 +81,8 @@ static void xio3130_downstream_realize(PCIDevice *d, Error
**errp)
goto err_bridge;
}
- rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
- XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
- errp);
- if (rc < 0) {
- goto err_msi;
- }
+ pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
+ XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
p->port, errp);
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index 5ff46ef050..d954906d79 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -71,12 +71,8 @@ static void xio3130_upstream_realize(PCIDevice *d, Error
**errp)
goto err_bridge;
}
- rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
- XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
- errp);
- if (rc < 0) {
- goto err_msi;
- }
+ pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
+ XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
p->port, errp);
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index da34c8ebcd..30032fed64 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -42,21 +42,15 @@
#define PCI_SSVID_SVID 4
#define PCI_SSVID_SSID 6
-int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
- uint16_t svid, uint16_t ssid,
- Error **errp)
+void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
+ uint16_t svid, uint16_t ssid)
{
- int pos;
+ uint8_t pos;
- pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
- PCI_SSVID_SIZEOF, errp);
- if (pos < 0) {
- return pos;
- }
+ pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
- return pos;
}
/* Accessor function to get parent bridge device from pci bus. */
@@ -455,11 +449,8 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int
cap_offset,
.mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64)
};
- int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
- cap_offset, cap_len, errp);
- if (offset < 0) {
- return offset;
- }
+ uint8_t offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
+ cap_offset, cap_len);
memcpy(dev->config + offset + PCI_CAP_FLAGS,
(char *)&cap + PCI_CAP_FLAGS,
diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
index ba4bafac7c..e499482972 100644
--- a/include/hw/pci/pci_bridge.h
+++ b/include/hw/pci/pci_bridge.h
@@ -101,9 +101,8 @@ typedef struct PXBDev PXBDev;
DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV,
TYPE_PXB_CXL_DEVICE)
-int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
- uint16_t svid, uint16_t ssid,
- Error **errp);
+void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
+ uint16_t svid, uint16_t ssid);
PCIDevice *pci_bridge_get_device(PCIBus *bus);
PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
--
2.37.3
- [PATCH v4 03/17] hw/i386/amd_iommu: Omit errp for pci_add_capability, (continued)
- [PATCH v4 03/17] hw/i386/amd_iommu: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 05/17] e1000e: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 07/17] hw/nvme: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 11/17] pci/shpc: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 06/17] eepro100: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 04/17] ahci: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 10/17] pcie: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 13/17] pci/slotid: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 12/17] msix: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 15/17] hw/vfio/pci: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 09/17] hw/pci/pci_bridge: Omit errp for pci_add_capability,
Akihiko Odaki <=
- [PATCH v4 08/17] msi: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 14/17] hw/pci-bridge/pcie_pci_bridge: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 16/17] virtio-pci: Omit errp for pci_add_capability, Akihiko Odaki, 2022/10/27
- [PATCH v4 17/17] pci: Remove legacy errp from pci_add_capability, Akihiko Odaki, 2022/10/27