Re: [PATCH 2/3] target/ppc: Add new PMC HFLAGS

[Daniel Henrique Barboza]

On 10/21/22 14:01, Leandro Lupori wrote:
> Add 2 new PMC related HFLAGS:
> - HFLAGS_PMCJCE - value of MMCR0 PMCjCE bit
> - HFLAGS_PMC_OTHER - set if a PMC other than PMC5-6 is enabled
>
> These flags allow further optimization of PMC5 update code, by
> allowing frequently tested conditions to be performed at
> translation time.
>
> Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   target/ppc/cpu.h         | 4 +++-
>   target/ppc/helper_regs.c | 6 ++++++
>   target/ppc/translate.c   | 4 ++++
>   3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index cca6c4e51c..28b9b8d4e3 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -696,7 +696,9 @@ enum {
>       HFLAGS_PR = 14,  /* MSR_PR */
>       HFLAGS_PMCC0 = 15,  /* MMCR0 PMCC bit 0 */
>       HFLAGS_PMCC1 = 16,  /* MMCR0 PMCC bit 1 */
> -    HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */
> +    HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
> +    HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
> +    HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
>       HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
>       HFLAGS_VR = 25,  /* MSR_VR if cpu has VRE */
>   
> diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
> index 12235ea2e9..65f5f7b2c0 100644
> --- a/target/ppc/helper_regs.c
> +++ b/target/ppc/helper_regs.c
> @@ -109,6 +109,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
>       if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
>           hflags |= 1 << HFLAGS_PMCC1;
>       }
> +    if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) {
> +        hflags |= 1 << HFLAGS_PMCJCE;
> +    }
>   
>   #ifndef CONFIG_USER_ONLY
>       if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
> @@ -119,6 +122,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
>       if (env->pmc_ins_cnt) {
>           hflags |= 1 << HFLAGS_INSN_CNT;
>       }
> +    if (env->pmc_ins_cnt & 0x1e) {
> +        hflags |= 1 << HFLAGS_PMC_OTHER;
> +    }
>   #endif
>   
>       /*
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index e810842925..8fda2cf836 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -177,6 +177,8 @@ struct DisasContext {
>       bool hr;
>       bool mmcr0_pmcc0;
>       bool mmcr0_pmcc1;
> +    bool mmcr0_pmcjce;
> +    bool pmc_other;
>       bool pmu_insn_cnt;
>       ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
>       int singlestep_enabled;
> @@ -7574,6 +7576,8 @@ static void ppc_tr_init_disas_context(DisasContextBase 
> *dcbase, CPUState *cs)
>       ctx->hr = (hflags >> HFLAGS_HR) & 1;
>       ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
>       ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
> +    ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1;
> +    ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1;
>       ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
>   
>       ctx->singlestep_enabled = 0;