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[PULL 19/30] target/arm: Implement FEAT_HAFDBS, dirty bit portion
From: |
Peter Maydell |
Subject: |
[PULL 19/30] target/arm: Implement FEAT_HAFDBS, dirty bit portion |
Date: |
Tue, 25 Oct 2022 17:39:41 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Perform the atomic update for hardware management of the dirty bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 2 +-
target/arm/ptw.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f2c3e41f5a7..3d74f134f57 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1165,7 +1165,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
- t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 1); /* FEAT_HAFDBS, AF only */
+ t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 03776f47a01..6b8f14fb3cd 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1444,6 +1444,22 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
goto do_fault;
}
}
+
+ /*
+ * Dirty Bit.
+ * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
+ * bit for writeback. The actual write protection test may still be
+ * overridden by tableattrs, to be merged below.
+ */
+ if (param.hd
+ && extract64(descriptor, 51, 1) /* DBM */
+ && access_type == MMU_DATA_STORE) {
+ if (regime_is_stage2(mmu_idx)) {
+ new_descriptor |= 1ull << 7; /* set S2AP[1] */
+ } else {
+ new_descriptor &= ~(1ull << 7); /* clear AP[2] */
+ }
+ }
}
/*
--
2.25.1
- [PULL 03/30] target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked(), (continued)
- [PULL 03/30] target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked(), Peter Maydell, 2022/10/25
- [PULL 10/30] target/arm: Extract HA and HD in aa64_va_parameters, Peter Maydell, 2022/10/25
- [PULL 11/30] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Peter Maydell, 2022/10/25
- [PULL 15/30] target/arm: Don't shift attrs in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 16/30] target/arm: Consider GP an attribute in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 14/30] target/arm: Fix fault reporting in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 17/30] target/arm: Tidy merging of attributes from descriptor and table, Peter Maydell, 2022/10/25
- [PULL 12/30] target/arm: Add ARMFault_UnsuppAtomicUpdate, Peter Maydell, 2022/10/25
- [PULL 13/30] target/arm: Remove loop from get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 18/30] target/arm: Implement FEAT_HAFDBS, access flag portion, Peter Maydell, 2022/10/25
- [PULL 19/30] target/arm: Implement FEAT_HAFDBS, dirty bit portion,
Peter Maydell <=
- [PULL 07/30] target/arm: Introduce regime_is_stage2, Peter Maydell, 2022/10/25
- [PULL 21/30] reset: allow registering handlers that aren't called by snapshot loading, Peter Maydell, 2022/10/25
- [PULL 23/30] x86: do not re-randomize RNG seed on snapshot load, Peter Maydell, 2022/10/25
- [PULL 28/30] mips/boston: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25
- [PULL 30/30] rx: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25
- [PULL 25/30] riscv: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25
- [PULL 29/30] openrisc: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25
- [PULL 24/30] arm: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25
- [PULL 20/30] target/arm: Use the max page size in a 2-stage ptw, Peter Maydell, 2022/10/25
- [PULL 22/30] device-tree: add re-randomization helper function, Peter Maydell, 2022/10/25