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[PULL 02/24] target/arm: update the cortex-a15 MIDR to latest rev
From: |
Peter Maydell |
Subject: |
[PULL 02/24] target/arm: update the cortex-a15 MIDR to latest rev |
Date: |
Thu, 20 Oct 2022 13:21:24 +0100 |
From: Alex Bennée <alex.bennee@linaro.org>
QEMU doesn't model micro-architectural details which includes most
chip errata. The ARM_ERRATA_798181 work around in the Linux
kernel (see erratum_a15_798181_init) currently detects QEMU's
cortex-a15 as broken and triggers additional expensive TLB flushes as
a result.
Change the MIDR to report what the latest silicon would (r4p0). We
explicitly set the IMPDEF revidr bits to 0 because we don't need to
set anything other than the silicon revision to indicate these flushes
are not needed. This cuts about 5s from my Debian kernel boot with the
latest 6.0rc1 kernel (29s->24s).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Message-id: 20221010153225.506394-1-alex.bennee@linaro.org
Cc: Arnd Bergmann <arnd@linaro.org>
Cc: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Message-Id: <20220906172257.2776521-1-alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu_tcg.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 98b5ba21604..60ff539fa18 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -592,7 +592,9 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
- cpu->midr = 0x412fc0f1;
+ /* r4p0 cpu, not requiring expensive tlb flush errata */
+ cpu->midr = 0x414fc0f0;
+ cpu->revidr = 0x0;
cpu->reset_fpsid = 0x410430f0;
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x11111111;
--
2.25.1
- [PULL 00/24] target-arm queue, Peter Maydell, 2022/10/20
- [PULL 01/24] hw/char/pl011: fix baud rate calculation, Peter Maydell, 2022/10/20
- [PULL 05/24] target/arm: Use probe_access_full for BTI, Peter Maydell, 2022/10/20
- [PULL 09/24] target/arm: Split out S1Translate type, Peter Maydell, 2022/10/20
- [PULL 03/24] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA, Peter Maydell, 2022/10/20
- [PULL 02/24] target/arm: update the cortex-a15 MIDR to latest rev,
Peter Maydell <=
- [PULL 23/24] target/arm: Enable TARGET_TB_PCREL, Peter Maydell, 2022/10/20
- [PULL 07/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Peter Maydell, 2022/10/20
- [PULL 11/24] target/arm: Move be test for regime into S1TranslateResult, Peter Maydell, 2022/10/20
- [PULL 06/24] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Peter Maydell, 2022/10/20
- [PULL 10/24] target/arm: Plumb debug into S1Translate, Peter Maydell, 2022/10/20
- [PULL 15/24] target/arm: Introduce curr_insn_len, Peter Maydell, 2022/10/20
- [PULL 17/24] target/arm: Change gen_*set_pc_im to gen_*update_pc, Peter Maydell, 2022/10/20
- [PULL 04/24] target/arm: Use probe_access_full for MTE, Peter Maydell, 2022/10/20
- [PULL 19/24] target/arm: Remove gen_exception_internal_insn pc argument, Peter Maydell, 2022/10/20
- [PULL 20/24] target/arm: Change gen_jmp* to work on displacements, Peter Maydell, 2022/10/20