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[PULL 23/53] target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext
From: |
Paolo Bonzini |
Subject: |
[PULL 23/53] target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext |
Date: |
Tue, 18 Oct 2022 15:30:12 +0200 |
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index eb174dbb8c..abccaadfbf 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -116,6 +116,7 @@ typedef struct DisasContext {
int cpuid_ext2_features;
int cpuid_ext3_features;
int cpuid_7_0_ebx_features;
+ int cpuid_7_0_ecx_features;
int cpuid_xsave_features;
/* TCG local temps */
@@ -8859,6 +8860,7 @@ static void i386_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
+ dc->cpuid_7_0_ecx_features = env->features[FEAT_7_0_ECX];
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
--
2.37.3
- [PULL 34/53] target/i386: Introduce 256-bit vector helpers, (continued)
- [PULL 34/53] target/i386: Introduce 256-bit vector helpers, Paolo Bonzini, 2022/10/18
- [PULL 25/53] target/i386: add AVX_EN hflag, Paolo Bonzini, 2022/10/18
- [PULL 24/53] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/10/18
- [PULL 41/53] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes, Paolo Bonzini, 2022/10/18
- [PULL 28/53] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/10/18
- [PULL 40/53] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 32/53] target/i386: provide 3-operand versions of unary scalar helpers, Paolo Bonzini, 2022/10/18
- [PULL 43/53] target/i386: Use tcg gvec ops for pmovmskb, Paolo Bonzini, 2022/10/18
- [PULL 36/53] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 35/53] target/i386: reimplement 0x0f 0x60-0x6f, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 23/53] target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext,
Paolo Bonzini <=
- [PULL 44/53] target/i386: reimplement 0x0f 0x38, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 53/53] target/i386: remove old SSE decoder, Paolo Bonzini, 2022/10/18
- [PULL 27/53] target/i386: validate SSE prefixes directly in the decoding table, Paolo Bonzini, 2022/10/18
- [PULL 37/53] target/i386: reimplement 0x0f 0x50-0x5f, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 26/53] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/10/18
- [PULL 29/53] target/i386: Prepare ops_sse_header.h for 256 bit AVX, Paolo Bonzini, 2022/10/18
- [PULL 30/53] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings, Paolo Bonzini, 2022/10/18
- [PULL 20/53] target/i386: make rex_w available even in 32-bit mode, Paolo Bonzini, 2022/10/18
- [PULL 45/53] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 47/53] target/i386: reimplement 0x0f 0x28-0x2f, add AVX, Paolo Bonzini, 2022/10/18