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[PATCH 16/35] target/i386: Introduce 256-bit vector helpers
From: |
Paolo Bonzini |
Subject: |
[PATCH 16/35] target/i386: Introduce 256-bit vector helpers |
Date: |
Thu, 13 Oct 2022 23:46:32 +0200 |
The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done. We just need to
build them.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/helper.h | 2 ++
target/i386/ops_sse.h | 5 +++++
target/i386/ops_sse_header.h | 4 ++++
target/i386/tcg/fpu_helper.c | 3 +++
4 files changed, 14 insertions(+)
diff --git a/target/i386/helper.h b/target/i386/helper.h
index 39a3c24182..a2c2c085a3 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -218,6 +218,8 @@ DEF_HELPER_3(movq, void, env, ptr, ptr)
#include "ops_sse_header.h"
#define SHIFT 1
#include "ops_sse_header.h"
+#define SHIFT 2
+#include "ops_sse_header.h"
DEF_HELPER_3(rclb, tl, env, tl, tl)
DEF_HELPER_3(rclw, tl, env, tl, tl)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 18d217ebf5..090ba013b3 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -35,7 +35,11 @@
#define W(n) ZMM_W(n)
#define L(n) ZMM_L(n)
#define Q(n) ZMM_Q(n)
+#if SHIFT == 1
#define SUFFIX _xmm
+#else
+#define SUFFIX _ymm
+#endif
#endif
#define LANE_WIDTH (SHIFT ? 16 : 8)
@@ -2379,6 +2383,7 @@ void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State
*env, Reg *d, Reg *s,
#undef SSE_HELPER_S
+#undef LANE_WIDTH
#undef SHIFT
#undef XMM_ONLY
#undef Reg
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index e7866a8395..440f1c0e78 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -21,7 +21,11 @@
#define SUFFIX _mmx
#else
#define Reg ZMMReg
+#if SHIFT == 1
#define SUFFIX _xmm
+#else
+#define SUFFIX _ymm
+#endif
#endif
#define dh_alias_Reg ptr
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 9b59026e37..5f3f7a1085 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -3065,3 +3065,6 @@ void helper_movq(CPUX86State *env, void *d, void *s)
#define SHIFT 1
#include "ops_sse.h"
+
+#define SHIFT 2
+#include "ops_sse.h"
--
2.37.3
- [PATCH v3 00/35] target/i386: new decoder + AVX implementation, Paolo Bonzini, 2022/10/13
- [PATCH 01/35] target/i386: Define XMMReg and access macros, align ZMM registers, Paolo Bonzini, 2022/10/13
- [PATCH 02/35] target/i386: make ldo/sto operations consistent with ldq, Paolo Bonzini, 2022/10/13
- [PATCH 05/35] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext, Paolo Bonzini, 2022/10/13
- [PATCH 06/35] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/10/13
- [PATCH 09/35] target/i386: validate SSE prefixes directly in the decoding table, Paolo Bonzini, 2022/10/13
- [PATCH 04/35] target/i386: add ALU load/writeback core, Paolo Bonzini, 2022/10/13
- [PATCH 03/35] target/i386: add core of new i386 decoder, Paolo Bonzini, 2022/10/13
- [PATCH 07/35] target/i386: add AVX_EN hflag, Paolo Bonzini, 2022/10/13
- [PATCH 10/35] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/10/13
- [PATCH 16/35] target/i386: Introduce 256-bit vector helpers,
Paolo Bonzini <=
- [PATCH 08/35] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/10/13
- [PATCH 13/35] target/i386: support operand merging in binary scalar helpers, Paolo Bonzini, 2022/10/13
- [PATCH 19/35] target/i386: reimplement 0x0f 0x50-0x5f, add AVX, Paolo Bonzini, 2022/10/13
- [PATCH 14/35] target/i386: provide 3-operand versions of unary scalar helpers, Paolo Bonzini, 2022/10/13
- [PATCH 28/35] target/i386: reimplement 0x0f 0x10-0x17, add AVX, Paolo Bonzini, 2022/10/13
- [PATCH 35/35] target/i386: remove old SSE decoder, Paolo Bonzini, 2022/10/13
- [PATCH 18/35] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX, Paolo Bonzini, 2022/10/13
- [PATCH 17/35] target/i386: reimplement 0x0f 0x60-0x6f, add AVX, Paolo Bonzini, 2022/10/13
- [PATCH 15/35] target/i386: implement additional AVX comparison operators, Paolo Bonzini, 2022/10/13
- [PATCH 20/35] target/i386: reimplement 0x0f 0x78-0x7f, add AVX, Paolo Bonzini, 2022/10/13