Re: [PATCH v10 3/5] target/riscv: generate virtual instruction exception

[weiwei]

On 2022/10/3 19:47, Mayuresh Chitale wrote:
> This patch adds a mechanism to generate a virtual instruction
> instruction exception instead of an illegal instruction exception
> during instruction decode when virt is enabled.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
>   target/riscv/translate.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index db123da5ec..6926b639de 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -76,6 +76,7 @@ typedef struct DisasContext {
>          to reset this known value.  */
>       int frm;
>       RISCVMXL ol;
> +    bool virt_inst_excp;
>       bool virt_enabled;
>       const RISCVCPUConfig *cfg_ptr;
>       bool hlsx;
> @@ -243,7 +244,11 @@ static void gen_exception_illegal(DisasContext *ctx)
>   {
>       tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
>                      offsetof(CPURISCVState, bins));
> -    generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> +    if (ctx->virt_inst_excp) {
> +        generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
> +    } else {
> +        generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> +    }
>   }
>   
>   static void gen_exception_inst_addr_mis(DisasContext *ctx)
> @@ -1067,6 +1072,7 @@ static void decode_opc(CPURISCVState *env, DisasContext 
> *ctx, uint16_t opcode)
>           if (!has_ext(ctx, RVC)) {
>               gen_exception_illegal(ctx);

I think we should also set virt_inst_excp to false before this 
gen_exception_illegal.

By the way, why not just put  "ctx->virt_inst_excp = false;" at the 
begin of the decode_opc?

Regards,

Weiwei Li

>           } else {
> +            ctx->virt_inst_excp = false;
>               ctx->opcode = opcode;
>               ctx->pc_succ_insn = ctx->base.pc_next + 2;
>               if (decode_insn16(ctx, opcode)) {
> @@ -1078,6 +1084,7 @@ static void decode_opc(CPURISCVState *env, DisasContext 
> *ctx, uint16_t opcode)
>           opcode32 = deposit32(opcode32, 16, 16,
>                                translator_lduw(env, &ctx->base,
>                                                ctx->base.pc_next + 2));
> +        ctx->virt_inst_excp = false;
>           ctx->opcode = opcode32;
>           ctx->pc_succ_insn = ctx->base.pc_next + 4;
>