Re: [PATCH] include/qemu/atomic128: Support 16-byte atomic read/write for Intel AVX

[Peter Maydell]

On Sat, 8 Oct 2022 at 16:38, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Intel has now given guarantees about the atomicity of SSE read
> and write instructions on cpus supporting AVX.  We can use these
> instead of the much slower cmpxchg16b.
>
> Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> +    /*
> +     * The xgetbv instruction is not available to older versions of
> +     * the assembler, so we encode the instruction manually.
> +     */
> +    asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0));

This would make the third place in the tree where we hand-code
this asm instruction (we already do it in the xgetbv() function
in target/i386/hvf/x86_cpuid.c and opencoded in tcg_target_init()):
can we abstract this out somehow, please?

(There is also a just-written-out "xgetbv" in init_cpuid_cache(),
but that one's guarded by ifdefs so presumably OK.)

thanks
-- PMM