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[PULL 11/20] accel/tcg: Use bool for page_find_alloc
From: |
Richard Henderson |
Subject: |
[PULL 11/20] accel/tcg: Use bool for page_find_alloc |
Date: |
Tue, 4 Oct 2022 12:52:32 -0700 |
Bool is more appropriate type for the alloc parameter.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/translate-all.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 59432dc558..ca685f6ede 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -465,7 +465,7 @@ void page_init(void)
#endif
}
-static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
+static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc)
{
PageDesc *pd;
void **lp;
@@ -533,11 +533,11 @@ static PageDesc *page_find_alloc(tb_page_addr_t index,
int alloc)
static inline PageDesc *page_find(tb_page_addr_t index)
{
- return page_find_alloc(index, 0);
+ return page_find_alloc(index, false);
}
static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
- PageDesc **ret_p2, tb_page_addr_t phys2, int alloc);
+ PageDesc **ret_p2, tb_page_addr_t phys2, bool
alloc);
/* In user-mode page locks aren't used; mmap_lock is enough */
#ifdef CONFIG_USER_ONLY
@@ -651,7 +651,7 @@ static inline void page_unlock(PageDesc *pd)
/* lock the page(s) of a TB in the correct acquisition order */
static inline void page_lock_tb(const TranslationBlock *tb)
{
- page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0);
+ page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false);
}
static inline void page_unlock_tb(const TranslationBlock *tb)
@@ -840,7 +840,7 @@ void page_collection_unlock(struct page_collection *set)
#endif /* !CONFIG_USER_ONLY */
static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
- PageDesc **ret_p2, tb_page_addr_t phys2, int alloc)
+ PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc)
{
PageDesc *p1, *p2;
tb_page_addr_t page1;
@@ -1290,7 +1290,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
* Note that inserting into the hash table first isn't an option, since
* we can only insert TBs that are fully initialized.
*/
- page_lock_pair(&p, phys_pc, &p2, phys_page2, 1);
+ page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
if (p2) {
tb_page_add(p2, tb, 1, phys_page2);
@@ -2219,7 +2219,7 @@ void page_set_flags(target_ulong start, target_ulong end,
int flags)
for (addr = start, len = end - start;
len != 0;
len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
- PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
+ PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, true);
/* If the write protection bit is set, then we invalidate
the code inside. */
--
2.34.1
- [PULL 00/20] tcg patch queue, Richard Henderson, 2022/10/04
- [PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB, Richard Henderson, 2022/10/04
- [PULL 03/20] cputlb: used cached CPUClass in our hot-paths, Richard Henderson, 2022/10/04
- [PULL 04/20] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/10/04
- [PULL 07/20] accel/tcg: Introduce probe_access_full, Richard Henderson, 2022/10/04
- [PULL 08/20] accel/tcg: Introduce tlb_set_page_full, Richard Henderson, 2022/10/04
- [PULL 02/20] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs, Richard Henderson, 2022/10/04
- [PULL 06/20] accel/tcg: Suppress auto-invalidate in probe_access_internal, Richard Henderson, 2022/10/04
- [PULL 11/20] accel/tcg: Use bool for page_find_alloc,
Richard Henderson <=
- [PULL 01/20] cpu: cache CPUClass in CPUState for hot code paths, Richard Henderson, 2022/10/04
- [PULL 09/20] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/10/04
- [PULL 10/20] accel/tcg: Remove PageDesc code_bitmap, Richard Henderson, 2022/10/04
- [PULL 12/20] accel/tcg: Use DisasContextBase in plugin_gen_tb_start, Richard Henderson, 2022/10/04
- [PULL 13/20] accel/tcg: Do not align tb->page_addr[0], Richard Henderson, 2022/10/04
- [PULL 14/20] accel/tcg: Inline tb_flush_jmp_cache, Richard Henderson, 2022/10/04
- [PULL 18/20] accel/tcg: Introduce TARGET_TB_PCREL, Richard Henderson, 2022/10/04
- [PULL 15/20] include/hw/core: Create struct CPUJumpCache, Richard Henderson, 2022/10/04