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[PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1
From: |
Richard Henderson |
Subject: |
[PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1 |
Date: |
Sat, 1 Oct 2022 09:22:53 -0700 |
Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so
that we use is_secure instead of the current security state.
These AT* operations have been broken since arm_hcr_el2_eff
gained a check for "el2 enabled" for Secure EL2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a0dce9c313..7bf79779da 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx,
}
}
- hcr_el2 = arm_hcr_el2_eff(env);
+ hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure);
switch (mmu_idx) {
case ARMMMUIdx_Stage2:
@@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx
mmu_idx,
return ~0;
}
- hcr = arm_hcr_el2_eff(env);
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
/*
* PTW set and S1 walk touched S2 Device memory:
@@ -2341,7 +2341,7 @@ bool get_phys_addr_with_secure(CPUARMState *env,
target_ulong address,
}
/* Combine the S1 and S2 cache attributes. */
- hcr = arm_hcr_el2_eff(env);
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
if (hcr & HCR_DC) {
/*
* HCR.DC forces the first stage attributes to
@@ -2474,7 +2474,7 @@ bool get_phys_addr_with_secure(CPUARMState *env,
target_ulong address,
result->page_size = TARGET_PAGE_SIZE;
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
- hcr = arm_hcr_el2_eff(env);
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
result->cacheattrs.shareability = 0;
result->cacheattrs.is_s2_format = false;
if (hcr & HCR_DC) {
--
2.34.1
- [PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate, (continued)
- [PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/10/01
- [PATCH v3 04/42] target/arm: Add is_secure parameter to regime_translation_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 05/42] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/10/01
- [PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/10/01
- [PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/10/01
- [PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/10/01
- [PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/10/01
- [PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/10/01
- [PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/10/01
- [PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1,
Richard Henderson <=
- [PATCH v3 18/42] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 12/42] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/10/01
- [PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/10/01
- [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 21/42] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/10/01
- [PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write, Richard Henderson, 2022/10/01
- [PATCH v3 22/42] target/arm: Use probe_access_full for MTE, Richard Henderson, 2022/10/01