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[PATCH v6 14/18] accel/tcg: Inline tb_flush_jmp_cache
From: |
Richard Henderson |
Subject: |
[PATCH v6 14/18] accel/tcg: Inline tb_flush_jmp_cache |
Date: |
Fri, 30 Sep 2022 14:26:18 -0700 |
This function has two users, who use it incompatibly.
In tlb_flush_page_by_mmuidx_async_0, when flushing a
single page, we need to flush exactly two pages.
In tlb_flush_range_by_mmuidx_async_0, when flushing a
range of pages, we need to flush N+1 pages.
This avoids double-flushing of jmp cache pages in a range.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a0db2d32a8..c7909fb619 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -107,14 +107,6 @@ static void tb_jmp_cache_clear_page(CPUState *cpu,
target_ulong page_addr)
}
}
-static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
-{
- /* Discard jump cache entries for any tb which might potentially
- overlap the flushed page. */
- tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
- tb_jmp_cache_clear_page(cpu, addr);
-}
-
/**
* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if
necessary
* @desc: The CPUTLBDesc portion of the TLB
@@ -541,7 +533,12 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,
}
qemu_spin_unlock(&env_tlb(env)->c.lock);
- tb_flush_jmp_cache(cpu, addr);
+ /*
+ * Discard jump cache entries for any tb which might potentially
+ * overlap the flushed page, which includes the previous.
+ */
+ tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
+ tb_jmp_cache_clear_page(cpu, addr);
}
/**
@@ -792,8 +789,14 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState
*cpu,
return;
}
- for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) {
- tb_flush_jmp_cache(cpu, d.addr + i);
+ /*
+ * Discard jump cache entries for any tb which might potentially
+ * overlap the flushed pages, which includes the previous.
+ */
+ d.addr -= TARGET_PAGE_SIZE;
+ for (target_ulong i = 0, n = d.len / TARGET_PAGE_SIZE + 1; i < n; i++) {
+ tb_jmp_cache_clear_page(cpu, d.addr);
+ d.addr += TARGET_PAGE_SIZE;
}
}
--
2.34.1
- [PATCH v6 04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, (continued)
- [PATCH v6 04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/09/30
- [PATCH v6 05/18] accel/tcg: Drop addr member from SavedIOTLB, Richard Henderson, 2022/09/30
- [PATCH v6 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal, Richard Henderson, 2022/09/30
- [PATCH v6 07/18] accel/tcg: Introduce probe_access_full, Richard Henderson, 2022/09/30
- [PATCH v6 08/18] accel/tcg: Introduce tlb_set_page_full, Richard Henderson, 2022/09/30
- [PATCH v6 09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/09/30
- [PATCH v6 10/18] accel/tcg: Remove PageDesc code_bitmap, Richard Henderson, 2022/09/30
- [PATCH v6 11/18] accel/tcg: Use bool for page_find_alloc, Richard Henderson, 2022/09/30
- [PATCH v6 13/18] accel/tcg: Do not align tb->page_addr[0], Richard Henderson, 2022/09/30
- [PATCH v6 12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start, Richard Henderson, 2022/09/30
- [PATCH v6 14/18] accel/tcg: Inline tb_flush_jmp_cache,
Richard Henderson <=
- [PATCH v6 15/18] include/hw/core: Create struct CPUJumpCache, Richard Henderson, 2022/09/30
- [PATCH v6 16/18] hw/core: Add CPUClass.get_pc, Richard Henderson, 2022/09/30
- [PATCH v6 18/18] accel/tcg: Introduce TARGET_TB_PCREL, Richard Henderson, 2022/09/30
- [PATCH v6 17/18] accel/tcg: Introduce tb_pc and log_pc, Richard Henderson, 2022/09/30
- Re: [PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL, Richard Henderson, 2022/09/30