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From: | Richard Henderson |
Subject: | Re: [PATCH v2] RISC-V: Add support for Ztso |
Date: | Sun, 25 Sep 2022 10:28:08 +0000 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 |
On 9/23/22 10:49, Palmer Dabbelt wrote:
The Ztso extension was recently frozen, this adds it as a CPU property and adds various fences throughout the port in order to allow TSO targets to function on weaker hosts. We need no fences for AMOs asthey're already SC, the placess we need barriers are described. These fences are placed in the RISC-V backend rather than TCG as is planned for x86-on-arm64 because RISC-V allows heterogenous (and likely soon dynamic) hart memory models.
Heterogenous shouldn't have been a problem (no more than Arm a-profile co-existing with m-profile), but dynamic would have been difficult to do generically for sure.
Otherwise this description addition looks good. r~
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