Re: [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues

[Alistair Francis]

On Wed, Sep 14, 2022 at 8:11 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
> ROM flow. This series makes it more configurguable from the command line
> and fixes the default.
>
> Alistair Francis (3):
>   target/riscv: Set the CPU resetvec directly
>   hw/riscv: opentitan: Fixup resetvec
>   hw/riscv: opentitan: Expose the resetvec as a SoC property

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  include/hw/riscv/opentitan.h |  2 ++
>  target/riscv/cpu.h           |  3 +--
>  hw/riscv/opentitan.c         |  8 +++++++-
>  target/riscv/cpu.c           | 13 +++----------
>  target/riscv/machine.c       |  6 +++---
>  5 files changed, 16 insertions(+), 16 deletions(-)
>
> --
> 2.37.2
>