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[PULL 13/20] target/arm: Honour MDCR_EL2.HPMD in Secure EL2
From: |
Richard Henderson |
Subject: |
[PULL 13/20] target/arm: Honour MDCR_EL2.HPMD in Secure EL2 |
Date: |
Wed, 14 Sep 2022 12:52:10 +0100 |
From: Peter Maydell <peter.maydell@linaro.org>
The logic in pmu_counter_enabled() for handling the 'prohibit event
counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way
that assumes that EL2 is never Secure. This used to be true, but the
architecture now permits Secure EL2, and QEMU can emulate this.
Refactor the prohibit logic so that we effectively OR together
the various prohibit bits when they apply, rather than trying to
construct an if-else ladder where any particular state of the CPU
ends up in exactly one branch of the ladder.
This fixes the Secure EL2 case and also is a better structure for
adding the PMUv8.5 bits MDCR_EL2.HCCD and MDCR_EL3.SCCD.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-6-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f1b20de16d..b792694df0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1094,7 +1094,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t
counter)
{
uint64_t filter;
bool e, p, u, nsk, nsu, nsh, m;
- bool enabled, prohibited, filtered;
+ bool enabled, prohibited = false, filtered;
bool secure = arm_is_secure(env);
int el = arm_current_el(env);
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
@@ -1112,15 +1112,12 @@ static bool pmu_counter_enabled(CPUARMState *env,
uint8_t counter)
}
enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
- if (!secure) {
- if (el == 2 && (counter < hpmn || counter == 31)) {
- prohibited = mdcr_el2 & MDCR_HPMD;
- } else {
- prohibited = false;
- }
- } else {
- prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
- !(env->cp15.mdcr_el3 & MDCR_SPME);
+ /* Is event counting prohibited? */
+ if (el == 2 && (counter < hpmn || counter == 31)) {
+ prohibited = mdcr_el2 & MDCR_HPMD;
+ }
+ if (secure) {
+ prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME);
}
if (prohibited && counter == 31) {
--
2.34.1
- Re: [PULL 11/20] target/arm: Don't mishandle count when enabling or disabling PMU counters, (continued)
- [PULL 14/20] target/arm: Detect overflow when calculating next PMU interrupt, Richard Henderson, 2022/09/14
- [PULL 16/20] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits, Richard Henderson, 2022/09/14
- [PULL 09/20] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows, Richard Henderson, 2022/09/14
- [PULL 08/20] target/arm: Add missing space in comment, Richard Henderson, 2022/09/14
- [PULL 12/20] target/arm: Ignore PMCR.D when PMCR.LC is set, Richard Henderson, 2022/09/14
- [PULL 10/20] target/arm: Correct value returned by pmu_counter_mask(), Richard Henderson, 2022/09/14
- [PULL 17/20] target/arm: Support 64-bit event counters for FEAT_PMUv3p5, Richard Henderson, 2022/09/14
- [PULL 18/20] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max', Richard Henderson, 2022/09/14
- [PULL 19/20] target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel(), Richard Henderson, 2022/09/14
- [PULL 13/20] target/arm: Honour MDCR_EL2.HPMD in Secure EL2,
Richard Henderson <=
- [PATCH] target/arm: Do alignment check when translation disabled, Richard Henderson, 2022/09/14
- [PULL 15/20] target/arm: Rename pmu_8_n feature test functions, Richard Henderson, 2022/09/14
- [PULL 20/20] target/arm: Make boards pass base address to armv7m_load_kernel(), Richard Henderson, 2022/09/14
- Re: [PULL 00/20] target-arm.next patch queue, Stefan Hajnoczi, 2022/09/17