Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions

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Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions

From:	Christoph Müllner
Subject:	Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions
Date:	Fri, 9 Sep 2022 19:21:34 +0200

On Thu, Sep 8, 2022 at 9:30 AM Richard Henderson <richard.henderson@linaro.org> wrote:

On 9/6/22 13:22, Christoph Muellner wrote:
> +NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU)
> +NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU)
> +NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU)
> +NOP_PRIVCHECK(th_sync_s, REQUIRE_PRIV_MHSU)

These should not be nops: th_sfence_vmas requires a tlb flush; th.sync{,.i} needs to end
the current translation block; th.sync.{s,is} needs multiprocessor sync, which involves a
call to async_safe_run_on_cpu.

Understood.

For a new revision, I'll do the following:

* th_sfence_vmas: async_safe_run_on_cpu() with run_on_cpu_func which flushes TLB on all CPUs (similar like trans_sfence_vma())

* th_sync/th_sync_i: end the TB (similar like trans_fence_i())

* th_sync_s/th_sync_is: async_safe_run_on_cpu() with run_on_cpu_func which ends the TB (similar like trans_fence_i())

Thanks!

r~

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[PATCH 00/11] Add support for the T-Head vendor extensions, Christoph Muellner, 2022/09/06
- [PATCH 01/11] riscv: Add privilege level to DisasContext, Christoph Muellner, 2022/09/06
  - Re: [PATCH 01/11] riscv: Add privilege level to DisasContext, LIU Zhiwei, 2022/09/15
  - Re: [PATCH 01/11] riscv: Add privilege level to DisasContext, Richard Henderson, 2022/09/16
    - Re: [PATCH 01/11] riscv: Add privilege level to DisasContext, Richard Henderson, 2022/09/16
    - Re: [PATCH 01/11] riscv: Add privilege level to DisasContext, LIU Zhiwei, 2022/09/16
- [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions, Christoph Muellner, 2022/09/06
  - Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions, Richard Henderson, 2022/09/08
    - Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions, Christoph Müllner <=
- [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions, Christoph Muellner, 2022/09/06
  - Re: [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions, LIU Zhiwei, 2022/09/16
- [PATCH 02/11] RISC-V: Adding T-Head CMO instructions, Christoph Muellner, 2022/09/06
  - Re: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions, LIU Zhiwei, 2022/09/15
  - Re: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions, LIU Zhiwei, 2022/09/16
    - Re: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions, Richard Henderson, 2022/09/16
- [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions, Christoph Muellner, 2022/09/06
- [PATCH 05/11] RISC-V: Adding T-Head CondMov instructions, Christoph Muellner, 2022/09/06
- [PATCH 07/11] RISC-V: Adding T-Head XMAE support, Christoph Muellner, 2022/09/06
- [PATCH 08/11] RISC-V: Adding T-Head MemPair extension, Christoph Muellner, 2022/09/06

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