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[PULL 22/39] target/i386: check SSE table flags instead of hardcoding op
From: |
Paolo Bonzini |
Subject: |
[PULL 22/39] target/i386: check SSE table flags instead of hardcoding opcodes |
Date: |
Thu, 1 Sep 2022 20:24:12 +0200 |
Put more flags to work to avoid hardcoding lists of opcodes. The op7 case
for SSE_OPF_CMP is included for homogeneity and because AVX needs it, but
it is never used by SSE or MMX.
Extracted from a patch by Paul Brook <paul@nowt.org>.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 75 +++++++++++++++----------------------
1 file changed, 31 insertions(+), 44 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index c76f6dba11..849c40b685 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3909,7 +3909,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
op6->op[b1](cpu_env, s->ptr0, s->ptr1);
- if (b == 0x17) {
+ if (op6->flags & SSE_OPF_CMP) {
set_cc_op(s, CC_OP_EFLAGS);
}
break;
@@ -4463,6 +4463,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
op7->op[b1](cpu_env, s->ptr0, s->ptr1, tcg_const_i32(val));
+ if (op7->flags & SSE_OPF_CMP) {
+ set_cc_op(s, CC_OP_EFLAGS);
+ }
break;
case 0x33a:
@@ -4518,28 +4521,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
int sz = 4;
gen_lea_modrm(env, s, modrm);
- op2_offset = offsetof(CPUX86State,xmm_t0);
+ op2_offset = offsetof(CPUX86State, xmm_t0);
- switch (b) {
- case 0x50 ... 0x5a:
- case 0x5c ... 0x5f:
- case 0xc2:
- /* Most sse scalar operations. */
- if (b1 == 2) {
- sz = 2;
- } else if (b1 == 3) {
- sz = 3;
- }
- break;
-
- case 0x2e: /* ucomis[sd] */
- case 0x2f: /* comis[sd] */
- if (b1 == 0) {
- sz = 2;
+ if (sse_op_flags & SSE_OPF_SCALAR) {
+ if (sse_op_flags & SSE_OPF_CMP) {
+ /* ucomis[sd], comis[sd] */
+ if (b1 == 0) {
+ sz = 2;
+ } else {
+ sz = 3;
+ }
} else {
- sz = 3;
+ /* Most sse scalar operations. */
+ if (b1 == 2) {
+ sz = 2;
+ } else if (b1 == 3) {
+ sz = 3;
+ }
}
- break;
}
switch (sz) {
@@ -4585,26 +4584,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
return;
}
}
- switch(b) {
- case 0x70: /* pshufx insn */
- case 0xc6: /* pshufx insn */
+ tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
+ tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
+ if (sse_op_flags & SSE_OPF_SHUF) {
val = x86_ldub_code(env, s);
- tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
- tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
/* XXX: introduce a new table? */
sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
sse_fn_ppi(s->ptr0, s->ptr1, tcg_const_i32(val));
- break;
- case 0xc2:
- /* compare insns, bits 7:3 (7:5 for AVX) are ignored */
- val = x86_ldub_code(env, s) & 7;
- sse_fn_epp = sse_op_table4[val][b1];
-
- tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
- tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
- sse_fn_epp(cpu_env, s->ptr0, s->ptr1);
- break;
- case 0xf7:
+ } else if (b == 0xf7) {
/* maskmov : we must prepare A0 */
if (mod != 3) {
goto illegal_op;
@@ -4613,19 +4600,19 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
gen_extu(s->aflag, s->A0);
gen_add_A0_ds_seg(s);
- tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
- tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
/* XXX: introduce a new table? */
sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
sse_fn_eppt(cpu_env, s->ptr0, s->ptr1, s->A0);
- break;
- default:
- tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
- tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
+ } else if (b == 0xc2) {
+ /* compare insns, bits 7:3 (7:5 for AVX) are ignored */
+ val = x86_ldub_code(env, s) & 7;
+ sse_fn_epp = sse_op_table4[val][b1];
+ sse_fn_epp(cpu_env, s->ptr0, s->ptr1);
+ } else {
sse_fn_epp(cpu_env, s->ptr0, s->ptr1);
- break;
}
- if (b == 0x2e || b == 0x2f) {
+
+ if (sse_op_flags & SSE_OPF_CMP) {
set_cc_op(s, CC_OP_EFLAGS);
}
}
--
2.37.2
- [PULL 09/39] meson: remove dead assignments, (continued)
- [PULL 09/39] meson: remove dead assignments, Paolo Bonzini, 2022/09/01
- [PULL 14/39] target/i386: DPPS rounding fix, Paolo Bonzini, 2022/09/01
- [PULL 12/39] tests/tcg: i386: extend BMI test, Paolo Bonzini, 2022/09/01
- [PULL 13/39] target/i386: fix PHSUB* instructions with dest=src, Paolo Bonzini, 2022/09/01
- [PULL 17/39] target/i386: formatting fixes, Paolo Bonzini, 2022/09/01
- [PULL 16/39] target/i386: do not use MOVL to move data between SSE registers, Paolo Bonzini, 2022/09/01
- [PULL 15/39] tests/tcg: i386: add SSE tests, Paolo Bonzini, 2022/09/01
- [PULL 19/39] target/i386: Rework sse_op_table1, Paolo Bonzini, 2022/09/01
- [PULL 21/39] target/i386: Move 3DNOW decoder, Paolo Bonzini, 2022/09/01
- [PULL 20/39] target/i386: Rework sse_op_table6/7, Paolo Bonzini, 2022/09/01
- [PULL 22/39] target/i386: check SSE table flags instead of hardcoding opcodes,
Paolo Bonzini <=
- [PULL 18/39] target/i386: Add ZMM_OFFSET macro, Paolo Bonzini, 2022/09/01
- [PULL 23/39] target/i386: isolate MMX code more, Paolo Bonzini, 2022/09/01
- [PULL 26/39] target/i386: Add CHECK_NO_VEX, Paolo Bonzini, 2022/09/01
- [PULL 27/39] target/i386: rewrite destructive 3DNow operations, Paolo Bonzini, 2022/09/01
- [PULL 25/39] target/i386: do not cast gen_helper_* function pointers, Paolo Bonzini, 2022/09/01
- [PULL 24/39] target/i386: Add size suffix to vector FP helpers, Paolo Bonzini, 2022/09/01
- [PULL 30/39] target/i386: Misc integer AVX helper prep, Paolo Bonzini, 2022/09/01
- [PULL 33/39] target/i386: reimplement AVX comparison helpers, Paolo Bonzini, 2022/09/01
- [PULL 31/39] target/i386: Destructive vector helpers for AVX, Paolo Bonzini, 2022/09/01
- [PULL 29/39] target/i386: Rewrite simple integer vector helpers, Paolo Bonzini, 2022/09/01