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[PATCH v1] target/riscv: Add xicondops in ISA entry
From: |
Rahul Pathak |
Subject: |
[PATCH v1] target/riscv: Add xicondops in ISA entry |
Date: |
Tue, 16 Aug 2022 10:24:08 +0530 |
XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
---
This patch is based on branch riscv-to-apply.next (Alistair qemu tree)
Based on top commit: f2a91d8b78
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2498b93105..27d10bd6a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -104,6 +104,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
};
static bool isa_ext_is_enabled(RISCVCPU *cpu,
--
2.34.1
- [PATCH v1] target/riscv: Add xicondops in ISA entry,
Rahul Pathak <=