On 8/8/22 14:16, BALATON Zoltan wrote:
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
Hello,
Here is large series QOM'ifying the PPC405 board. It introduces a new
generic machine and SoC models, converts the current device models to
QOM and populates the SoC. The process is quite mechanical without too
much issues to handle. The noisy part is the initial patch introducing
the SoC realize routine.
What's left ?
* the SDRAM mappings are very baroque and certainly could be simplified.
I think we should QOMify the ppc440 machines before addressing this
part.
The issue with SDRAM controller and the likely reason why its model looks
so complex is that it can't handle any RAM size because of how the bank
sizes are encoded in the registers so it only really supports real RAM
modules which are predefined sizes. Also the firmware discovers RAM by
looking at SPD data and may only check the slots that the real hardware has
which may not be the first one.
Previously I had code to round down the memory size specified on the
command line to an acceptable size and issue a warning to let the user know
but this was dropped because of some changes in code elsewhere which now
allocates memory before the machine could check and ajust it so we can only
adjust it by wasting some.
I don't think we should care adjusting the values. the machine init
routine should check that the RAM size is valid or fail. The machine
should also have a sane RAM size value by default.
See how the aspeed machine deals with similar constraints of its SDRAM
controller in aspeed_machine_init(). If the sdram controller does not
validate the RAM size, aspeed_sdmc_set_ram_size() fails with an error.