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[PULL 0/1] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
[PULL 0/1] riscv-to-apply queue |
Date: |
Tue, 2 Aug 2022 09:02:11 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
The following changes since commit 0e0c2cf6de0bc6538840837c63b25817cd417347:
Merge tag 'pull-target-arm-20220801' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-08-01
12:00:08 -0700)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220802
for you to fetch changes up to 1eaa63429a9944265c92efdb94c02fabb231f564:
linux-user/riscv: Align signal frame to 16 bytes (2022-08-02 08:56:49 +1000)
----------------------------------------------------------------
Seventh RISC-V PR for QEMU 7.1
This is a second PR to go in for RC1. It fixes a bug we have had
for awhile, but it's a simple fix so let's pull it in for RC1.
* linux-user/riscv: Align signal frame to 16 bytes
----------------------------------------------------------------
Richard Henderson (1):
linux-user/riscv: Align signal frame to 16 bytes
linux-user/riscv/signal.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
- [PULL 0/1] riscv-to-apply queue,
Alistair Francis <=