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[PULL 03/16] hw/i386/pc: Always place CXL Memory Regions after device_me
From: |
Michael S. Tsirkin |
Subject: |
[PULL 03/16] hw/i386/pc: Always place CXL Memory Regions after device_memory |
Date: |
Tue, 26 Jul 2022 15:40:31 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Previously broken_reserved_end was taken into account, but Igor Mammedov
identified that this could lead to a clash between potential RAM being
mapped in the region and CXL usage. Hence always add the size of the
device_memory memory region. This only affects the case where the
broken_reserved_end flag was set.
Fixes: 6e4e3ae936e6 ("hw/cxl/component: Implement host bridge MMIO (8.2.5,
table 142)")
Reported-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220701132300.2264-3-Jonathan.Cameron@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index d2b5823ffb..46ab1dcb47 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -922,10 +922,8 @@ void pc_memory_init(PCMachineState *pcms,
hwaddr cxl_size = MiB;
if (pcmc->has_reserved_memory && machine->device_memory->base) {
- cxl_base = machine->device_memory->base;
- if (!pcmc->broken_reserved_end) {
- cxl_base += memory_region_size(&machine->device_memory->mr);
- }
+ cxl_base = machine->device_memory->base
+ + memory_region_size(&machine->device_memory->mr);
} else if (pcms->sgx_epc.size != 0) {
cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc);
} else {
--
MST
- [PULL 00/16] pc,virtio: fixes, Michael S. Tsirkin, 2022/07/26
- [PULL 01/16] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug(), Michael S. Tsirkin, 2022/07/26
- [PULL 02/16] hw/machine: Clear out left over CXL related pointer from move of state handling to machines., Michael S. Tsirkin, 2022/07/26
- [PULL 03/16] hw/i386/pc: Always place CXL Memory Regions after device_memory,
Michael S. Tsirkin <=
- [PULL 05/16] hw/i386: add 4g boundary start to X86MachineState, Michael S. Tsirkin, 2022/07/26
- [PULL 06/16] i386/pc: create pci-host qdev prior to pc_memory_init(), Michael S. Tsirkin, 2022/07/26
- [PULL 04/16] hw/cxl: Fix size of constant in interleave granularity function., Michael S. Tsirkin, 2022/07/26
- [PULL 07/16] i386/pc: pass pci_hole64_size to pc_memory_init(), Michael S. Tsirkin, 2022/07/26
- [PULL 09/16] i386/pc: factor out cxl range end to helper, Michael S. Tsirkin, 2022/07/26
- [PULL 10/16] i386/pc: factor out cxl range start to helper, Michael S. Tsirkin, 2022/07/26
- [PULL 08/16] i386/pc: factor out above-4g end to an helper, Michael S. Tsirkin, 2022/07/26
- [PULL 11/16] i386/pc: handle unitialized mr in pc_get_cxl_range_end(), Michael S. Tsirkin, 2022/07/26
- [PULL 13/16] i386/pc: bounds check phys-bits against max used GPA, Michael S. Tsirkin, 2022/07/26
- [PULL 14/16] i386/pc: relocate 4g start to 1T where applicable, Michael S. Tsirkin, 2022/07/26