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[PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME
From: |
Peter Maydell |
Subject: |
[PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME |
Date: |
Mon, 18 Jul 2022 14:59:08 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We were only checking for SVE disabled and not taking into
account PSTATE.SM to check SME disabled, which resulted in
vectors being incorrectly truncated.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220713045848.217364-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 31 +++++++++++++++++++++++++------
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6fff7fc64fd..24c45a9bf31 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11228,6 +11228,21 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned
vq)
}
}
+static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm)
+{
+ int exc_el;
+
+ if (sm) {
+ exc_el = sme_exception_el(env, el);
+ } else {
+ exc_el = sve_exception_el(env, el);
+ }
+ if (exc_el) {
+ return 0; /* disabled */
+ }
+ return sve_vqm1_for_el_sm(env, el, sm);
+}
+
/*
* Notice a change in SVE vector size when changing EL.
*/
@@ -11236,7 +11251,7 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
{
ARMCPU *cpu = env_archcpu(env);
int old_len, new_len;
- bool old_a64, new_a64;
+ bool old_a64, new_a64, sm;
/* Nothing to do if no SVE. */
if (!cpu_isar_feature(aa64_sve, cpu)) {
@@ -11256,7 +11271,8 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
* invoke ResetSVEState when taking an exception from, or
* returning to, AArch32 state when PSTATE.SM is enabled.
*/
- if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) {
+ sm = FIELD_EX64(env->svcr, SVCR, SM);
+ if (old_a64 != new_a64 && sm) {
arm_reset_sve_state(env);
return;
}
@@ -11273,10 +11289,13 @@ void aarch64_sve_change_el(CPUARMState *env, int
old_el,
* we already have the correct register contents when encountering the
* vq0->vq0 transition between EL0->EL1.
*/
- old_len = (old_a64 && !sve_exception_el(env, old_el)
- ? sve_vqm1_for_el(env, old_el) : 0);
- new_len = (new_a64 && !sve_exception_el(env, new_el)
- ? sve_vqm1_for_el(env, new_el) : 0);
+ old_len = new_len = 0;
+ if (old_a64) {
+ old_len = sve_vqm1_for_el_sm_ena(env, old_el, sm);
+ }
+ if (new_a64) {
+ new_len = sve_vqm1_for_el_sm_ena(env, new_el, sm);
+ }
/* When changing vector length, clear inaccessible state. */
if (new_len < old_len) {
--
2.25.1
- [PULL 00/15] target-arm queue, Peter Maydell, 2022/07/18
- [PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high, Peter Maydell, 2022/07/18
- [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME,
Peter Maydell <=
- [PULL 05/15] target/arm: Define and use new regime_tcr_value() function, Peter Maydell, 2022/07/18
- [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register, Peter Maydell, 2022/07/18
- [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect, Peter Maydell, 2022/07/18
- [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled, Peter Maydell, 2022/07/18
- [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 08/15] target/arm: Fix big-endian host handling of VTCR, Peter Maydell, 2022/07/18
- [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address(), Peter Maydell, 2022/07/18
- [PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2, Peter Maydell, 2022/07/18
- [PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback, Peter Maydell, 2022/07/18