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[PATCH 5/7] pci: designware: move msi to entry 5
From: |
Ben Dooks |
Subject: |
[PATCH 5/7] pci: designware: move msi to entry 5 |
Date: |
Wed, 13 Jul 2022 17:54:47 +0100 |
The driver should leave irq[0..3] for INT[A..D] but seems to put the
MSI IRQ at entry 3 which should also be INT_D. Extend the irqs[] array
to 5 entires and put the MSI at entry irqs[4].
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
hw/pci-host/designware.c | 2 +-
include/hw/pci-host/designware.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 947547d153..b5d5b2b8a5 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -56,7 +56,7 @@
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
#define DESIGNWARE_PCIE_ATU_UPPER_LIMIT 0x924
-#define DESIGNWARE_PCIE_IRQ_MSI 3
+#define DESIGNWARE_PCIE_IRQ_MSI 4
static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index bd4dd49aec..37f90c5000 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -90,7 +90,7 @@ struct DesignwarePCIEHost {
MemoryRegion memory;
MemoryRegion io;
- qemu_irq irqs[4];
+ qemu_irq irqs[5];
} pci;
MemoryRegion mmio;
--
2.35.1
- updates for designware pci-host, Ben Dooks, 2022/07/13
- [PATCH 7/7] pci: designware: add initial tracing events, Ben Dooks, 2022/07/13
- [PATCH 3/7] pci: designware: clamp viewport index, Ben Dooks, 2022/07/13
- [PATCH 1/7] pci: designware: add 64-bit viewport limit, Ben Dooks, 2022/07/13
- [PATCH 5/7] pci: designware: move msi to entry 5,
Ben Dooks <=
- [PATCH 6/7] pci: designware: correct host's class_id, Ben Dooks, 2022/07/13
- [PATCH 2/7] pci: designware: fix DESIGNWARE_PCIE_ATU_UPPER_TARGET, Ben Dooks, 2022/07/13
- [PATCH 4/7] pci: designware: ignore new bits in ATU CR1, Ben Dooks, 2022/07/13
- Re: updates for designware pci-host, Ben Dooks, 2022/07/27