[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/19] aspeed: Create SRAM name from first CPU index
From: |
Cédric Le Goater |
Subject: |
[PULL 05/19] aspeed: Create SRAM name from first CPU index |
Date: |
Wed, 13 Jul 2022 09:52:41 +0200 |
From: Peter Delevoryas <peter@pjd.dev>
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM region though, for VM
migration. Since each of the SoC's CPU's has an index which identifies it
uniquely from other CPU's in the machine, we can use the index of any of the
CPU's in the SoC to uniquely identify differentiate the SRAM name from other
SoC SRAM's. In this change, I just elected to use the index of the first CPU
in each SoC.
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-3-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed_ast10x0.c | 5 ++++-
hw/arm/aspeed_ast2600.c | 5 +++--
hw/arm/aspeed_soc.c | 5 +++--
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 33ef33177199..677699e54c0a 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -159,6 +159,7 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
DeviceState *armv7m;
Error *err = NULL;
int i;
+ g_autofree char *sram_name = NULL;
if (!clock_has_source(s->sysclk)) {
error_setg(errp, "sysclk clock must be wired up by the board code");
@@ -183,7 +184,9 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
/* Internal SRAM */
- memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
+ sram_name = g_strdup_printf("aspeed.sram.%d",
+ CPU(s->armv7m.cpu)->cpu_index);
+ memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
&err);
if (err != NULL) {
error_propagate(errp, err);
return;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 3f0611ac11cd..64eb5a7b2600 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -276,6 +276,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
qemu_irq irq;
+ g_autofree char *sram_name = NULL;
/* IO space */
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
@@ -335,8 +336,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
}
/* SRAM */
- memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
- sc->sram_size, &err);
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+ memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
&err);
if (err) {
error_propagate(errp, err);
return;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 0f675e7fcdf5..0bb6a2f092c9 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -239,6 +239,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
+ g_autofree char *sram_name = NULL;
/* IO space */
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
@@ -259,8 +260,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
}
/* SRAM */
- memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
- sc->sram_size, &err);
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+ memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
&err);
if (err) {
error_propagate(errp, err);
return;
--
2.35.3
- [PULL 00/19] aspeed queue, Cédric Le Goater, 2022/07/13
- [PULL 02/19] hw/i2c/pmbus: Add idle state to return 0xff's, Cédric Le Goater, 2022/07/13
- [PULL 01/19] aspeed: sbc: Allow per-machine settings, Cédric Le Goater, 2022/07/13
- [PULL 03/19] hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators, Cédric Le Goater, 2022/07/13
- [PULL 04/19] hw/sensor: Add Renesas ISL69259 device model, Cédric Le Goater, 2022/07/13
- [PULL 06/19] aspeed: Refactor UART init for multi-SoC machines, Cédric Le Goater, 2022/07/13
- [PULL 07/19] aspeed: Make aspeed_board_init_flashes public, Cédric Le Goater, 2022/07/13
- [PULL 14/19] test/avocado/machine_aspeed.py: Add SDK tests, Cédric Le Goater, 2022/07/13
- [PULL 10/19] aspeed: fby35: Add a bootrom for the BMC, Cédric Le Goater, 2022/07/13
- [PULL 13/19] docs: aspeed: Minor updates, Cédric Le Goater, 2022/07/13
- [PULL 05/19] aspeed: Create SRAM name from first CPU index,
Cédric Le Goater <=
- [PULL 08/19] aspeed: Add fby35 skeleton, Cédric Le Goater, 2022/07/13
- [PULL 09/19] aspeed: Add AST2600 (BMC) to fby35, Cédric Le Goater, 2022/07/13
- [PULL 11/19] aspeed: Add AST1030 (BIC) to fby35, Cédric Le Goater, 2022/07/13
- [PULL 12/19] docs: aspeed: Add fby35 multi-SoC machine section, Cédric Le Goater, 2022/07/13
- [PULL 16/19] hw: m25p80: add tests for BP and TB bit write protect, Cédric Le Goater, 2022/07/13
- [PULL 15/19] hw: m25p80: Add Block Protect and Top Bottom bits for write protect, Cédric Le Goater, 2022/07/13
- [PULL 18/19] hw/gpio/aspeed: Don't let guests modify input pins, Cédric Le Goater, 2022/07/13
- [PULL 17/19] qtest/aspeed_gpio: Add input pin modification test, Cédric Le Goater, 2022/07/13
- [PULL 19/19] aspeed: Add fby35-bmc slot GPIO's, Cédric Le Goater, 2022/07/13
- Re: [PULL 00/19] aspeed queue, Peter Maydell, 2022/07/14