Re: [PATCH] target/riscv: fix user-mode build issue because mhartid

[Rahul Pathak]

Hi Bin, Victor,

Going to send the v2 by fixing these
silly mistakes.

Thanks
Rahul

On Mon, Jun 27, 2022 at 7:59 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 5:40 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
> >
> > mhartid csr is not available in user-mode code path and
> > user-mode build fails because of its reference in
> > riscv_cpu_realize function
> >
>
> Normally a "Fixes" tag should be added, but see below:
>
> > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> > ---
> >  target/riscv/cpu.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 0a794ef622..03f23d4b6d 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -643,9 +643,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> > **errp)
> >          if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
> >              (env->priv_ver < isa_edata_arr[i].min_version)) {
> >              isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
> > +#ifndef CONFIG_USER_ONLY
> >              warn_report("disabling %s extension for hart 0x%lx because "
> >                          "privilege spec version does not match",
> >                          isa_edata_arr[i].name, (unsigned 
> > long)env->mhartid);
>
> I can't find this in the mainline codes, so I assume this code exists
> in Alistair's tree?
>
> If that, please indicate in the commit message that this patch should
> be squashed into the offending commit in Alistair's tree.
>
> > +#else
> > +            warn_report("disabling %s extension for hart 0x%lx because "
> > +                        "privilege spec version does not match",
> > +                        isa_edata_arr[i].name);
> > +#endif
>
> Regards,
> Bin



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