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[PULL 24/25] target/arm: Extend arm_pamax to more than aarch64
From: |
Peter Maydell |
Subject: |
[PULL 24/25] target/arm: Extend arm_pamax to more than aarch64 |
Date: |
Mon, 27 Jun 2022 11:22:35 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Move the code from hw/arm/virt.c that is supposed
to handle v7 into the one function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: He Zhe <zhe.he@windriver.com>
Message-id: 20220619001541.131672-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 10 +---------
target/arm/ptw.c | 24 ++++++++++++++++--------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 097238faa7a..5502aa60c83 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2010,15 +2010,7 @@ static void machvirt_init(MachineState *machine)
cpuobj = object_new(possible_cpus->cpus[0].type);
armcpu = ARM_CPU(cpuobj);
- if (object_property_get_bool(cpuobj, "aarch64", NULL)) {
- pa_bits = arm_pamax(armcpu);
- } else if (arm_feature(&armcpu->env, ARM_FEATURE_LPAE)) {
- /* v7 with LPAE */
- pa_bits = 40;
- } else {
- /* Anything else */
- pa_bits = 32;
- }
+ pa_bits = arm_pamax(armcpu);
object_unref(cpuobj);
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 4d97a248084..07f7a218611 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -36,15 +36,23 @@ static const uint8_t pamax_map[] = {
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
unsigned int arm_pamax(ARMCPU *cpu)
{
- unsigned int parange =
- FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ unsigned int parange =
+ FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
- /*
- * id_aa64mmfr0 is a read-only register so values outside of the
- * supported mappings can be considered an implementation error.
- */
- assert(parange < ARRAY_SIZE(pamax_map));
- return pamax_map[parange];
+ /*
+ * id_aa64mmfr0 is a read-only register so values outside of the
+ * supported mappings can be considered an implementation error.
+ */
+ assert(parange < ARRAY_SIZE(pamax_map));
+ return pamax_map[parange];
+ }
+ if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
+ /* v7 with LPAE */
+ return 40;
+ }
+ /* Anything else */
+ return 32;
}
/*
--
2.25.1
- [PULL 18/25] target/arm: Move arm_cpu_*_finalize to internals.h, (continued)
- [PULL 18/25] target/arm: Move arm_cpu_*_finalize to internals.h, Peter Maydell, 2022/06/27
- [PULL 19/25] target/arm: Unexport aarch64_add_*_properties, Peter Maydell, 2022/06/27
- [PULL 21/25] target/arm: Introduce sve_vqm1_for_el_sm, Peter Maydell, 2022/06/27
- [PULL 20/25] target/arm: Add cpu properties for SME, Peter Maydell, 2022/06/27
- [PULL 23/25] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h, Peter Maydell, 2022/06/27
- [PULL 25/25] target/arm: Check V7VE as well as LPAE in arm_pamax, Peter Maydell, 2022/06/27
- [PULL 03/25] target/arm: Catch invalid kvm state also for hvf, Peter Maydell, 2022/06/27
- [PULL 08/25] target/arm: Add SVCR, Peter Maydell, 2022/06/27
- [PULL 22/25] target/arm: Add SVL to TB flags, Peter Maydell, 2022/06/27
- [PULL 14/25] target/arm: Move error for sve%d property to arm_cpu_sve_finalize, Peter Maydell, 2022/06/27
- [PULL 24/25] target/arm: Extend arm_pamax to more than aarch64,
Peter Maydell <=
- Re: [PULL 00/25] target-arm queue, Richard Henderson, 2022/06/27