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[PULL 15/25] target/arm: Create ARMVQMap
From: |
Peter Maydell |
Subject: |
[PULL 15/25] target/arm: Create ARMVQMap |
Date: |
Mon, 27 Jun 2022 11:22:26 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Pull the three sve_vq_* values into a structure.
This will be reused for SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 29 ++++++++++++++---------------
target/arm/cpu64.c | 22 +++++++++++-----------
target/arm/helper.c | 2 +-
target/arm/kvm64.c | 2 +-
4 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5877d76c9f3..2ce47f8d29f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -807,6 +807,19 @@ typedef enum ARMPSCIState {
typedef struct ARMISARegisters ARMISARegisters;
+/*
+ * In map, each set bit is a supported vector length of (bit-number + 1) * 16
+ * bytes, i.e. each bit number + 1 is the vector length in quadwords.
+ *
+ * While processing properties during initialization, corresponding init bits
+ * are set for bits in sve_vq_map that have been set by properties.
+ *
+ * Bits set in supported represent valid vector lengths for the CPU type.
+ */
+typedef struct {
+ uint32_t map, init, supported;
+} ARMVQMap;
+
/**
* ARMCPU:
* @env: #CPUARMState
@@ -1055,21 +1068,7 @@ struct ArchCPU {
uint32_t sve_default_vq;
#endif
- /*
- * In sve_vq_map each set bit is a supported vector length of
- * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
- * length in quadwords.
- *
- * While processing properties during initialization, corresponding
- * sve_vq_init bits are set for bits in sve_vq_map that have been
- * set by properties.
- *
- * Bits set in sve_vq_supported represent valid vector lengths for
- * the CPU type.
- */
- uint32_t sve_vq_map;
- uint32_t sve_vq_init;
- uint32_t sve_vq_supported;
+ ARMVQMap sve_vq;
/* Generic timer counter frequency, in Hz */
uint64_t gt_cntfrq_hz;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a46e40f4f2f..cadc401c7e0 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -355,8 +355,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
* any of the above. Finally, if SVE is not disabled, then at least one
* vector length must be enabled.
*/
- uint32_t vq_map = cpu->sve_vq_map;
- uint32_t vq_init = cpu->sve_vq_init;
+ uint32_t vq_map = cpu->sve_vq.map;
+ uint32_t vq_init = cpu->sve_vq.init;
uint32_t vq_supported;
uint32_t vq_mask = 0;
uint32_t tmp, vq, max_vq = 0;
@@ -369,14 +369,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
*/
if (kvm_enabled()) {
if (kvm_arm_sve_supported()) {
- cpu->sve_vq_supported = kvm_arm_sve_get_vls(CPU(cpu));
- vq_supported = cpu->sve_vq_supported;
+ cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu));
+ vq_supported = cpu->sve_vq.supported;
} else {
assert(!cpu_isar_feature(aa64_sve, cpu));
vq_supported = 0;
}
} else {
- vq_supported = cpu->sve_vq_supported;
+ vq_supported = cpu->sve_vq.supported;
}
/*
@@ -534,7 +534,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
/* From now on sve_max_vq is the actual maximum supported length. */
cpu->sve_max_vq = max_vq;
- cpu->sve_vq_map = vq_map;
+ cpu->sve_vq.map = vq_map;
}
static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
@@ -595,7 +595,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v,
const char *name,
if (!cpu_isar_feature(aa64_sve, cpu)) {
value = false;
} else {
- value = extract32(cpu->sve_vq_map, vq - 1, 1);
+ value = extract32(cpu->sve_vq.map, vq - 1, 1);
}
visit_type_bool(v, name, &value, errp);
}
@@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v,
const char *name,
return;
}
- cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value);
- cpu->sve_vq_init |= 1 << (vq - 1);
+ cpu->sve_vq.map = deposit32(cpu->sve_vq.map, vq - 1, 1, value);
+ cpu->sve_vq.init |= 1 << (vq - 1);
}
static bool cpu_arm_get_sve(Object *obj, Error **errp)
@@ -974,7 +974,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->dcz_blocksize = 7; /* 512 bytes */
#endif
- cpu->sve_vq_supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
+ cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
aarch64_add_pauth_properties(obj);
aarch64_add_sve_properties(obj);
@@ -1023,7 +1023,7 @@ static void aarch64_a64fx_initfn(Object *obj)
/* The A64FX supports only 128, 256 and 512 bit vector lengths */
aarch64_add_sve_properties(obj);
- cpu->sve_vq_supported = (1 << 0) /* 128bit */
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
| (1 << 1) /* 256bit */
| (1 << 3); /* 512bit */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 88d96f7991f..a80ca461e53 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6287,7 +6287,7 @@ uint32_t sve_vqm1_for_el(CPUARMState *env, int el)
len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
}
- len = 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1));
+ len = 31 - clz32(cpu->sve_vq.map & MAKE_64BIT_MASK(0, len + 1));
return len;
}
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index ff8f65da22f..d16d4ea2500 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -820,7 +820,7 @@ uint32_t kvm_arm_sve_get_vls(CPUState *cs)
static int kvm_arm_sve_set_vls(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
- uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq_map };
+ uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
struct kvm_one_reg reg = {
.id = KVM_REG_ARM64_SVE_VLS,
.addr = (uint64_t)&vls[0],
--
2.25.1
- [PULL 00/25] target-arm queue, Peter Maydell, 2022/06/27
- [PULL 07/25] target/arm: Add ARM_CP_SME, Peter Maydell, 2022/06/27
- [PULL 02/25] accel: Introduce current_accel_name(), Peter Maydell, 2022/06/27
- [PULL 10/25] target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2, Peter Maydell, 2022/06/27
- [PULL 04/25] target/arm: Implement TPIDR2_EL0, Peter Maydell, 2022/06/27
- [PULL 06/25] target/arm: Add syn_smetrap, Peter Maydell, 2022/06/27
- [PULL 11/25] target/arm: Add PSTATE.{SM,ZA} to TB flags, Peter Maydell, 2022/06/27
- [PULL 12/25] target/arm: Add the SME ZA storage to CPUARMState, Peter Maydell, 2022/06/27
- [PULL 16/25] target/arm: Generalize cpu_arm_{get,set}_vq, Peter Maydell, 2022/06/27
- [PULL 15/25] target/arm: Create ARMVQMap,
Peter Maydell <=
- [PULL 05/25] target/arm: Add SMEEXC_EL to TB flags, Peter Maydell, 2022/06/27
- [PULL 09/25] target/arm: Add SMCR_ELx, Peter Maydell, 2022/06/27
- [PULL 13/25] target/arm: Implement SMSTART, SMSTOP, Peter Maydell, 2022/06/27
- [PULL 17/25] target/arm: Generalize cpu_arm_{get, set}_default_vec_len, Peter Maydell, 2022/06/27
- [PULL 01/25] sphinx: change default language to 'en', Peter Maydell, 2022/06/27
- [PULL 18/25] target/arm: Move arm_cpu_*_finalize to internals.h, Peter Maydell, 2022/06/27
- [PULL 19/25] target/arm: Unexport aarch64_add_*_properties, Peter Maydell, 2022/06/27
- [PULL 21/25] target/arm: Introduce sve_vqm1_for_el_sm, Peter Maydell, 2022/06/27
- [PULL 20/25] target/arm: Add cpu properties for SME, Peter Maydell, 2022/06/27
- [PULL 23/25] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h, Peter Maydell, 2022/06/27