Re: [PATCH v3 23/51] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

[Peter Maydell]

On Wed, 22 Jun 2022 at 01:58, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 6/21/22 10:23, Peter Maydell wrote:
> >> +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a)
> >> +{
> >> +    if (!dc_isar_feature(aa64_sme, s)) {
> >> +        return false;
> >> +    }
> >> +    if (sme_enabled_check(s)) {
> >> +        TCGv_i64 reg = cpu_reg(s, a->rd);
> >> +        tcg_gen_movi_i64(reg, a->imm * s->svl);
> >> +    }
> >> +    return true;
> >> +}
> >
> > I think we should define functions that parallel the SVE
> > vec_full_reg_size() and pred_full_reg_size() rather than directly
> > looking at s->svl, for consistency with how we did the SVE code.
>
> I had actually been thinking of removing vec_full_reg_size, at least within 
> SVE.
> However... done.  I've propagated the new predicates forward through the 
> following patches
> as well.

I don't strongly care whether we use vec_full_reg_size() or
look at s->vl, as long as we do the same thing in both SVE
and SME.

I do think that it's worth wrapping up the '/ 8' in a
function that describes what it's doing, so the other
option I guess would be to use s->vl and s->svl directly
when we want the vector length, and have a function like

/* Predicates have 1 bit per byte in the vector */
static int veclen_to_predlen(int veclen)
{
    return veclen / 8;
}

and then use veclen_to_predlen(s->svl);
(Adjust function name, types, / 8 vs >> 3, to taste.)

thanks
-- PMM