Re: [PATCH v3 09/51] target/arm: Add the SME ZA storage to CPUARMState

[Peter Maydell]

On Mon, 20 Jun 2022 at 18:52, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Place this late in the resettable section of the structure,
> to keep the most common element offsets from being > 64k.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> +
> +    /*
> +     * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
> +     * as we do with vfp.zregs[].  Because this is so large, keep this toward
> +     * the end of the reset area, to keep the offsets into the rest of the
> +     * structure smaller.
> +     */
> +    ARMVectorReg zarray[ARM_MAX_VQ * 16];

Suggested more detailed comment:

    /*
     * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
     * as we do with vfp.zregs[]. This corresponds to the architectural ZA
     * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
     * When SVL is less than the architectural maximum, the accessible
     * storage is restricted, such that if the SVL is X bytes the guest can
     * see only the bottom X elements of zarray[], and only the least
significant
     * X bytes of each element of the array. (In other words, the
observable part
     * is always square.)
     *
     * The ZA storage can also be considered as a set of square tiles
of elements
     * of different sizes. The mapping from tiles to the ZA array is
architecturally
     * defined, such that for tiles of elements of esz bytes, the Nth row (or
     * "horizontal slice") of tile T is in ZA[T + N * esz]. Note that this means
     * that each tile is not contiguous in the ZA storage because its rows are
     * striped through the ZA array.
     *
     * Because the ZA storage is so large, keep this toward the end of the reset
     * area, to keep the offsets into the rest of the structure smaller.
     */

Arguably para 2 is repeating architectural information, but I think it's
helpful as a brief summary (compare the comment earlier in this file about
mappings between S, D and Q views of the vector registers).

thanks
-- PMM